drm2/i915/intel_display.c

500 		/* BIOS should set the proper LVDS register value at boot, but
501 		 * in reality, it doesn't set the value when the lid is closed;
502 		 * we need to check "the value to be set" in VBT when LVDS
641  * Returns whether the given set of divisors are valid for a given refclk with
690 		 * reliably set up different single/dual channel state, if we
984 	/* Wait for vblank interrupt bit to set */
1724 	/* Workaround: set timing override bit. */
2909 	/* still set train pattern 1 */
3143 	/* set transcoder timing, panel must allow it */
3316 			DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3886 		     "encoder->connectors_active not set\n");
4085  * set of depths.  Resolve that here:
4088  *    Displays may support a restricted set as well, check EDID and clamp as
4327 	/* set the corresponsding LVDS_BORDER bit */
4330 	 * set the DPLLs for dual-channel mode or not.
4337 	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4341 	/* set the dithering flag on LVDS as needed */
4734 	 * Returns a set of divisors for the desired target clock with the given
5290 	 * Returns a set of divisors for the desired target clock with the given
5443 	/* CPU eDP doesn't require FDI link, so just set DP M/N
5684 		/* set the corresponsding LVDS_BORDER bit */
5687 		 * set the DPLLs for dual-channel mode or not.
5694 		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5890 			/* set the corresponsding LVDS_BORDER bit */
5893 			 * we're going to set the DPLLs for dual-channel mode or
5902 			/* It would be nice to set 24 vs 18-bit mode
6004 		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6585  * Get a pipe with a simple mode set on it for doing load-based monitor
6598 /* VESA 640x480x72Hz mode to set on the pipe */
6787 		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7684 	 * bit set at most. */
7858 		     "encoder's active_connectors set, but no crtc\n");
7940 	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7951 	 * Hence simply check whether any bit is set in modeset_pipes in all the
7968 	 * to set it here already despite that we pass it down the callchain.
7991 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
8088 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8094 	if (set->crtc->fb != set->fb) {
8095 		/* If we have no fb then treat it as a full mode set */
8096 		if (set->crtc->fb == NULL) {
8097 			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8099 		} else if (set->fb == NULL) {
8101 		} else if (set->fb->depth != set->crtc->fb->depth) {
8103 		} else if (set->fb->bits_per_pixel !=
8104 			   set->crtc->fb->bits_per_pixel) {
8110 	if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8113 	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8114 		DRM_DEBUG_KMS("modes are different, full mode set\n");
8115 		drm_mode_debug_printmodeline(&set->crtc->mode);
8116 		drm_mode_debug_printmodeline(set->mode);
8123 				 struct drm_mode_set *set,
8133 	WARN_ON(!set->fb && (set->num_connectors != 0));
8134 	WARN_ON(set->fb && (set->num_connectors == 0));
8141 		for (ro = 0; ro < set->num_connectors; ro++) {
8142 			if (set->connectors[ro] == &connector->base) {
8151 		if ((!set->fb || ro == set->num_connectors) &&
8153 		    connector->base.encoder->crtc == set->crtc) {
8178 		for (ro = 0; ro < set->num_connectors; ro++) {
8179 			if (set->connectors[ro] == &connector->base)
8180 				new_crtc = set->crtc;
8222 static int intel_crtc_set_config(struct drm_mode_set *set)
8229 	BUG_ON(!set);
8230 	BUG_ON(!set->crtc);
8231 	BUG_ON(!set->crtc->helper_private);
8233 	if (!set->mode)
8234 		set->fb = NULL;
8239 	if (set->fb && set->num_connectors == 0)
8242 	if (set->fb) {
8244 				set->crtc->base.id, set->fb->base.id,
8245 				(int)set->num_connectors, set->x, set->y);
8247 		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8250 	dev = set->crtc->dev;
8261 	save_set.crtc = set->crtc;
8262 	save_set.mode = &set->crtc->mode;
8263 	save_set.x = set->crtc->x;
8264 	save_set.y = set->crtc->y;
8265 	save_set.fb = set->crtc->fb;
8271 	intel_set_config_compute_mode_changes(set, config);
8273 	ret = intel_modeset_stage_output_state(dev, set, config);
8278 		if (set->mode) {
8279 			DRM_DEBUG_KMS("attempting to set mode from"
8281 			drm_mode_debug_printmodeline(set->mode);
8284 		if (!intel_set_mode(set->crtc, set->mode,
8285 				    set->x, set->y, set->fb)) {
8286 			DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8287 				  set->crtc->base.id);
8292 		ret = intel_pipe_set_base(set->crtc,
8293 					  set->x, set->y, set->fb);
9064 	/* We can't just switch on the pipe A, we need to set things up with a
9439  * set vga decode state - true == enable VGA decode