drm2/i915/intel_display.c

1235 			 enum plane plane, bool state)
1241 	reg = DSPCNTR(plane);
1245 	     "plane %c assertion failure (expected %s, current %s)\n",
1246 	     plane_name(plane), state_string(state), state_string(cur_state));
1264 		     "plane %c assertion failure, should be disabled but not\n",
1276 		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
1435  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1820 	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1849  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1887 				      enum plane plane)
1890 		I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1892 		I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1896  * intel_enable_plane - enable a display plane on a given pipe
1898  * @plane: plane to enable
1901  * Enable @plane on @pipe, making sure that @pipe is running first.
1904 			       enum plane plane, enum pipe pipe)
1912 	reg = DSPCNTR(plane);
1918 	intel_flush_display_plane(dev_priv, plane);
1923  * intel_disable_plane - disable a display plane
1925  * @plane: plane to disable
1928  * Disable @plane; should be an independent operation.
1931 				enum plane plane, enum pipe pipe)
1936 	reg = DSPCNTR(plane);
1942 	intel_flush_display_plane(dev_priv, plane);
2043 	int plane = intel_crtc->plane;
2048 	switch (plane) {
2053 		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2060 	reg = DSPCNTR(plane);
2119 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2121 		I915_MODIFY_DISPBASE(DSPSURF(plane),
2123 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2124 		I915_WRITE(DSPLINOFF(plane), linear_offset);
2126 		I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2140 	int plane = intel_crtc->plane;
2145 	switch (plane) {
2151 		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2158 	reg = DSPCNTR(plane);
2209 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2210 	I915_MODIFY_DISPBASE(DSPSURF(plane),
2213 		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2215 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2216 		I915_WRITE(DSPLINOFF(plane), linear_offset);
2313 	if(intel_crtc->plane > dev_priv->num_pipe) {
2314 		DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2315 				intel_crtc->plane,
2467 	int plane = intel_crtc->plane;
2470 	/* FDI needs bits from pipe & plane first */
2472 	assert_plane_enabled(dev_priv, plane);
3327 	int plane = intel_crtc->plane;
3385 	intel_enable_plane(dev_priv, plane, pipe);
3420 	int plane = intel_crtc->plane;
3465 	intel_enable_plane(dev_priv, plane, pipe);
3497 	int plane = intel_crtc->plane;
3511 	intel_disable_plane(dev_priv, plane, pipe);
3513 	if (dev_priv->cfb_plane == plane)
3577 	int plane = intel_crtc->plane;
3593 	intel_disable_plane(dev_priv, plane, pipe);
3595 	if (dev_priv->cfb_plane == plane)
3667 	int plane = intel_crtc->plane;
3679 	intel_enable_plane(dev_priv, plane, pipe);
3699 	int plane = intel_crtc->plane;
3715 	if (dev_priv->cfb_plane == plane)
3718 	intel_disable_plane(dev_priv, plane, pipe);
3769  * Sets the power management mode of the pipe and plane.
3806 	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4699 	int plane = intel_crtc->plane;
4782 	/* Set up the display plane register */
4847 	I915_WRITE(DSPSIZE(plane),
4850 	I915_WRITE(DSPPOS(plane), 0);
4858 	I915_WRITE(DSPCNTR(plane), dspcntr);
4859 	POSTING_READ(DSPCNTR(plane));
5596 	int plane = intel_crtc->plane;
5756 	/* Set up the display plane register */
5757 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5758 	POSTING_READ(DSPCNTR(plane));
5779 	int plane = intel_crtc->plane;
5823 	WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5967 	/* Set up the display plane register */
5968 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5969 	POSTING_READ(DSPCNTR(plane));
6767 	 * that the plane may generate whilst we perform load detection.
7130 	atomic_clear_mask(1 << intel_crtc->plane,
7136 	CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
7148 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7151 	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7156 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7160 		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7162 	/* NB: An MMIO update of the plane base pointer will also
7203 	if (intel_crtc->plane)
7210 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7244 	if (intel_crtc->plane)
7251 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7290 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7334 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7379 	switch(intel_crtc->plane) {
7390 		WARN_ONCE(1, "unknown plane in flip command\n");
7493 	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7504 	CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
7511 	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7991 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
8367 	intel_crtc->plane = pipe;
8371 		intel_crtc->plane = !pipe;
8375 	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8376 	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8645 	/* Reject formats not supported by any plane early. */
8955 /* Disable the VGA plane that we never use */
9038 			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9094 	reg = DSPCNTR(!crtc->plane);
9114 	/* We need to sanitize the plane -> pipe mapping first because this will
9116 	 * that gen4+ has a fixed plane -> pipe mapping.  */
9119 		bool plane;
9121 		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9124 		/* Pipe has the wrong plane attached and the plane is active.
9125 		 * Temporarily change the plane mapping and disable everything
9127 		plane = crtc->plane;
9128 		crtc->plane = !plane;
9130 		crtc->plane = plane;
9239 		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9486 	} plane[I915_MAX_PIPES];
9508 		error->plane[i].control = I915_READ(DSPCNTR(i));
9509 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9510 		error->plane[i].size = I915_READ(DSPSIZE(i));
9511 		error->plane[i].pos = I915_READ(DSPPOS(i));
9512 		error->plane[i].addr = I915_READ(DSPADDR(i));
9514 			error->plane[i].surface = I915_READ(DSPSURF(i));
9515 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9552 		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9553 		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9554 		seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9555 		seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9556 		seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9558 			seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9559 			seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);