Lines Matching refs:pipe
625 * Returns whether any output on the specified pipe is of the specified type
931 enum pipe pipe)
933 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
939 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
942 u32 frame, frame_reg = PIPEFRAME(pipe);
951 * intel_wait_for_vblank - wait for vblank on a given pipe
953 * @pipe: pipe to wait for
955 * Wait for vblank to occur on a given pipe. Needed for various bits of
958 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
961 int pipestat_reg = PIPESTAT(pipe);
964 ironlake_wait_for_vblank(dev, pipe);
992 * intel_wait_for_pipe_off - wait for pipe to turn off
994 * @pipe: pipe to wait for
996 * After disabling a pipe, we can't wait for vblank in the usual way,
998 * see an interrupt when the pipe is disabled.
1001 * wait for the pipe register state bit to turn off
1008 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1012 pipe);
1023 int reg = PIPEDSL(pipe);
1049 enum pipe pipe, bool state)
1055 reg = DPLL(pipe);
1095 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1097 cur_state, crtc->pipe, pch_dpll)) {
1098 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 crtc->pipe,
1112 enum pipe pipe, bool state)
1118 pipe);
1126 reg = FDI_TX_CTL(pipe);
1138 enum pipe pipe, bool state)
1144 reg = FDI_RX_CTL(pipe);
1155 enum pipe pipe)
1168 reg = FDI_TX_CTL(pipe);
1174 enum pipe pipe)
1179 reg = FDI_RX_CTL(pipe);
1185 enum pipe pipe)
1189 enum pipe panel_pipe = PIPE_A;
1208 WARN(panel_pipe == pipe && locked,
1209 "panel assertion failure, pipe %c regs locked\n",
1210 pipe_name(pipe));
1214 enum pipe pipe, bool state)
1220 pipe);
1222 /* if we need the pipe A quirk it must be always on */
1223 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1230 "pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe), state_string(state), state_string(cur_state));
1253 enum pipe pipe)
1261 reg = DSPCNTR(pipe);
1265 plane_name(pipe));
1269 /* Need to check both planes against the pipe */
1275 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1276 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1277 plane_name(i), pipe_name(pipe));
1298 enum pipe pipe)
1304 reg = TRANSCONF(pipe);
1308 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1309 pipe_name(pipe));
1313 enum pipe pipe, u32 port_sel, u32 val)
1319 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1324 if ((val & DP_PIPE_MASK) != (pipe << 30))
1331 enum pipe pipe, u32 val)
1337 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1340 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1347 enum pipe pipe, u32 val)
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1363 enum pipe pipe, u32 val)
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1378 enum pipe pipe, int reg, u32 port_sel)
1381 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 reg, pipe_name(pipe));
1391 enum pipe pipe, int reg)
1394 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 reg, pipe_name(pipe));
1404 enum pipe pipe)
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1415 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1417 pipe_name(pipe));
1421 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1423 pipe_name(pipe));
1425 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1426 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1427 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1433 * @pipe: pipe PLL to enable
1435 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1443 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1453 assert_panel_unlocked(dev_priv, pipe);
1455 reg = DPLL(pipe);
1474 * @pipe: pipe PLL to disable
1476 * Disable the PLL for @pipe, making sure the pipe is off first.
1480 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1485 /* Don't disable pipe A or pipe A PLLs if needed */
1486 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1489 /* Make sure the pipe isn't still relying on us */
1490 assert_pipe_disabled(dev_priv, pipe);
1492 reg = DPLL(pipe);
1567 * @pipe: pipe PLL to enable
1644 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1657 enum pipe pipe)
1660 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1672 assert_fdi_tx_enabled(dev_priv, pipe);
1673 assert_fdi_rx_enabled(dev_priv, pipe);
1678 reg = TRANS_CHICKEN2(pipe);
1684 reg = TRANSCONF(pipe);
1686 pipeconf_val = I915_READ(PIPECONF(pipe));
1709 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1721 assert_fdi_tx_enabled(dev_priv, (enum pipe)cpu_transcoder);
1722 assert_fdi_rx_enabled(dev_priv, (enum pipe)TRANSCODER_A);
1744 enum pipe pipe)
1750 assert_fdi_tx_disabled(dev_priv, pipe);
1751 assert_fdi_rx_disabled(dev_priv, pipe);
1754 assert_pch_ports_disabled(dev_priv, pipe);
1756 reg = TRANSCONF(pipe);
1762 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1766 reg = TRANS_CHICKEN2(pipe);
1791 * intel_enable_pipe - enable a pipe, asserting requirements
1793 * @pipe: pipe to enable
1794 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1796 * Enable @pipe, making sure that various hardware specific requirements
1799 * @pipe should be %PIPE_A or %PIPE_B.
1801 * Will wait until the pipe is actually running (i.e. first vblank) before
1804 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1808 pipe);
1816 pch_transcoder = (enum transcoder)pipe;
1819 * A pipe without a PLL won't actually be able to drive bits from
1820 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1824 assert_pll_enabled(dev_priv, pipe);
1828 assert_fdi_rx_pll_enabled(dev_priv, (enum pipe)pch_transcoder);
1829 assert_fdi_tx_pll_enabled(dev_priv, (enum pipe)cpu_transcoder);
1840 intel_wait_for_vblank(dev_priv->dev, pipe);
1844 * intel_disable_pipe - disable a pipe, asserting requirements
1846 * @pipe: pipe to disable
1848 * Disable @pipe, making sure that various hardware specific requirements
1851 * @pipe should be %PIPE_A or %PIPE_B.
1853 * Will wait until the pipe has shut down before returning.
1856 enum pipe pipe)
1859 pipe);
1867 assert_planes_disabled(dev_priv, pipe);
1869 /* Don't disable pipe A or pipe A PLLs if needed */
1870 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1879 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1896 * intel_enable_plane - enable a display plane on a given pipe
1899 * @pipe: pipe being fed
1901 * Enable @plane on @pipe, making sure that @pipe is running first.
1904 enum plane plane, enum pipe pipe)
1909 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1910 assert_pipe_enabled(dev_priv, pipe);
1919 intel_wait_for_vblank(dev_priv->dev, pipe);
1926 * @pipe: pipe consuming the data
1931 enum plane plane, enum pipe pipe)
1943 intel_wait_for_vblank(dev_priv->dev, pipe);
2283 switch (intel_crtc->pipe) {
2347 intel_wait_for_vblank(dev, intel_crtc->pipe);
2401 int pipe = intel_crtc->pipe;
2405 reg = FDI_TX_CTL(pipe);
2416 reg = FDI_RX_CTL(pipe);
2447 * with all lanes. XXX: This misses the case where a pipe is not using
2466 int pipe = intel_crtc->pipe;
2470 /* FDI needs bits from pipe & plane first */
2471 assert_pipe_enabled(dev_priv, pipe);
2476 reg = FDI_RX_IMR(pipe);
2485 reg = FDI_TX_CTL(pipe);
2493 reg = FDI_RX_CTL(pipe);
2503 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2504 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2507 reg = FDI_RX_IIR(pipe);
2522 reg = FDI_TX_CTL(pipe);
2528 reg = FDI_RX_CTL(pipe);
2537 reg = FDI_RX_IIR(pipe);
2568 int pipe = intel_crtc->pipe;
2573 reg = FDI_RX_IMR(pipe);
2583 reg = FDI_TX_CTL(pipe);
2594 I915_WRITE(FDI_RX_MISC(pipe),
2597 reg = FDI_RX_CTL(pipe);
2612 reg = FDI_TX_CTL(pipe);
2622 reg = FDI_RX_IIR(pipe);
2639 reg = FDI_TX_CTL(pipe);
2650 reg = FDI_RX_CTL(pipe);
2665 reg = FDI_TX_CTL(pipe);
2675 reg = FDI_RX_IIR(pipe);
2700 int pipe = intel_crtc->pipe;
2705 reg = FDI_RX_IMR(pipe);
2715 I915_READ(FDI_RX_IIR(pipe)));
2718 reg = FDI_TX_CTL(pipe);
2729 I915_WRITE(FDI_RX_MISC(pipe),
2732 reg = FDI_RX_CTL(pipe);
2744 reg = FDI_TX_CTL(pipe);
2753 reg = FDI_RX_IIR(pipe);
2768 reg = FDI_TX_CTL(pipe);
2776 reg = FDI_RX_CTL(pipe);
2786 reg = FDI_TX_CTL(pipe);
2795 reg = FDI_RX_IIR(pipe);
2815 int pipe = intel_crtc->pipe;
2820 reg = FDI_RX_CTL(pipe);
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2841 reg = FDI_TX_CTL(pipe);
2856 int pipe = intel_crtc->pipe;
2860 reg = FDI_RX_CTL(pipe);
2865 reg = FDI_TX_CTL(pipe);
2872 reg = FDI_RX_CTL(pipe);
2886 int pipe = intel_crtc->pipe;
2890 reg = FDI_TX_CTL(pipe);
2895 reg = FDI_RX_CTL(pipe);
2898 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2906 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2910 reg = FDI_TX_CTL(pipe);
2916 reg = FDI_RX_CTL(pipe);
2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
3095 int pipe = intel_crtc->pipe;
3098 assert_transcoder_disabled(dev_priv, pipe);
3102 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3103 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3121 switch (pipe) {
3144 assert_panel_unlocked(dev_priv, pipe);
3145 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3146 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3147 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3149 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3150 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3151 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3152 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3160 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3161 reg = TRANS_DP_CTL(pipe);
3192 ironlake_enable_pch_transcoder(dev_priv, pipe);
3202 assert_transcoder_disabled(dev_priv, (enum pipe)TRANSCODER_A);
3249 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3250 i = intel_crtc->pipe;
3291 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3306 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3309 int dslreg = PIPEDSL(pipe);
3316 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3326 int pipe = intel_crtc->pipe;
3353 assert_fdi_tx_disabled(dev_priv, pipe);
3354 assert_fdi_rx_disabled(dev_priv, pipe);
3370 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3371 PF_PIPE_SEL_IVB(pipe));
3373 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3374 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3375 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3379 * On ILK+ LUT must be loaded before the pipe is running but with
3384 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3385 intel_enable_plane(dev_priv, plane, pipe);
3400 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3404 * outputs) where an enabled pipe still completes any pageflip right
3405 * away (as if the pipe is off) instead of waiting for vblank. As soon
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3419 int pipe = intel_crtc->pipe;
3449 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3450 PF_PIPE_SEL_IVB(pipe));
3451 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3452 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3456 * On ILK+ LUT must be loaded before the pipe is running but with
3464 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3465 intel_enable_plane(dev_priv, plane, pipe);
3481 * outputs) where an enabled pipe still completes any pageflip right
3482 * away (as if the pipe is off) instead of waiting for vblank. As soon
3487 intel_wait_for_vblank(dev, intel_crtc->pipe);
3496 int pipe = intel_crtc->pipe;
3508 drm_vblank_off(dev, pipe);
3511 intel_disable_plane(dev_priv, plane, pipe);
3516 intel_disable_pipe(dev_priv, pipe);
3519 I915_WRITE(PF_CTL(pipe), 0);
3520 I915_WRITE(PF_WIN_SZ(pipe), 0);
3528 ironlake_disable_pch_transcoder(dev_priv, pipe);
3532 reg = TRANS_DP_CTL(pipe);
3540 switch (pipe) {
3576 int pipe = intel_crtc->pipe;
3590 drm_vblank_off(dev, pipe);
3593 intel_disable_plane(dev_priv, plane, pipe);
3598 intel_disable_pipe(dev_priv, pipe);
3603 I915_WRITE(PF_CTL(pipe), 0);
3604 I915_WRITE(PF_WIN_SZ(pipe), 0);
3637 intel_crtc->cpu_transcoder = (enum transcoder)intel_crtc->pipe;
3666 int pipe = intel_crtc->pipe;
3677 intel_enable_pll(dev_priv, pipe);
3678 intel_enable_pipe(dev_priv, pipe, false);
3679 intel_enable_plane(dev_priv, plane, pipe);
3684 /* Give the overlay scaler a chance to enable if it's on this pipe */
3698 int pipe = intel_crtc->pipe;
3709 /* Give the overlay scaler a chance to disable if it's on this pipe */
3711 drm_vblank_off(dev, pipe);
3718 intel_disable_plane(dev_priv, plane, pipe);
3719 intel_disable_pipe(dev_priv, pipe);
3721 /* Disable pannel fitter if it is on this pipe. */
3724 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3727 intel_disable_pll(dev_priv, pipe);
3744 int pipe = intel_crtc->pipe;
3753 switch (pipe) {
3763 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3769 * Sets the power management mode of the pipe and plane.
3807 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3853 * state of the entire output pipe. */
3875 enum pipe pipe;
3888 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3897 WARN(pipe != to_intel_crtc(crtc)->pipe,
3898 "encoder active on the wrong pipe\n");
3931 enum pipe pipe = 0;
3934 return encoder->get_hw_state(encoder, &pipe);
4076 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4080 * A pipe may be connected to one or more outputs. Based on the depth of the
4081 * attached framebuffer, choose a good color depth to use on the pipe.
4083 * If possible, match the pipe depth to the fb depth. In some cases, this
4093 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4172 * We could just drive the pipe at the highest bpc all the time and
4203 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4284 int pipe = intel_crtc->pipe;
4299 I915_WRITE(FP0(pipe), fp);
4304 I915_WRITE(FP1(pipe), fp2);
4307 I915_WRITE(FP1(pipe), fp);
4317 int pipe = intel_crtc->pipe;
4322 if (pipe == 1) {
4365 int pipe = intel_crtc->pipe;
4379 I915_WRITE(DPLL(pipe), dpll);
4380 POSTING_READ(DPLL(pipe));
4398 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4400 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4406 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4408 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4411 I915_WRITE(DPLL(pipe), dpll);
4412 POSTING_READ(DPLL(pipe));
4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4414 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4421 I915_WRITE(DPLL(pipe), dpll);
4424 POSTING_READ(DPLL(pipe));
4435 I915_WRITE(DPLL_MD(pipe), temp);
4436 POSTING_READ(DPLL_MD(pipe));
4443 if(pipe == 1)
4450 if(pipe == 1)
4465 int pipe = intel_crtc->pipe;
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530 POSTING_READ(DPLL(pipe));
4543 I915_WRITE(DPLL(pipe), dpll);
4546 POSTING_READ(DPLL(pipe));
4558 I915_WRITE(DPLL_MD(pipe), temp);
4565 I915_WRITE(DPLL(pipe), dpll);
4577 int pipe = intel_crtc->pipe;
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4607 POSTING_READ(DPLL(pipe));
4617 I915_WRITE(DPLL(pipe), dpll);
4620 POSTING_READ(DPLL(pipe));
4628 I915_WRITE(DPLL(pipe), dpll);
4637 enum pipe pipe = intel_crtc->pipe;
4679 (pipe == PIPE_B || pipe == PIPE_C))
4680 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4685 I915_WRITE(PIPESRC(pipe),
4698 int pipe = intel_crtc->pipe;
4780 pipeconf = I915_READ(PIPECONF(pipe));
4785 if (pipe == 0)
4790 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795 * pipe == 0 check?
4822 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4852 I915_WRITE(PIPECONF(pipe), pipeconf);
4853 POSTING_READ(PIPECONF(pipe));
4854 intel_enable_pipe(dev_priv, pipe, false);
4856 intel_wait_for_vblank(dev, pipe);
5194 int pipe = intel_crtc->pipe;
5197 val = I915_READ(PIPECONF(pipe));
5228 I915_WRITE(PIPECONF(pipe), val);
5229 POSTING_READ(PIPECONF(pipe));
5345 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5346 intel_crtc->pipe, intel_crtc->fdi_lanes);
5348 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5349 intel_crtc->pipe, intel_crtc->fdi_lanes);
5359 switch (intel_crtc->pipe) {
5365 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5366 intel_crtc->pipe, intel_crtc->fdi_lanes);
5382 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5383 intel_crtc->pipe, intel_crtc->fdi_lanes);
5595 int pipe = intel_crtc->pipe;
5651 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5660 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5661 pipe);
5676 temp |= PORT_TRANS_SEL_CPT(pipe);
5678 if (pipe == 1)
5710 I915_WRITE(TRANSDATA_M1(pipe), 0);
5711 I915_WRITE(TRANSDATA_N1(pipe), 0);
5712 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5713 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5754 intel_wait_for_vblank(dev, pipe);
5764 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5778 int pipe = intel_crtc->pipe;
5811 intel_crtc->cpu_transcoder = pipe;
5817 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5818 num_connectors, pipe_name(pipe));
5847 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5866 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5867 pipe);
5882 temp |= PORT_TRANS_SEL_CPT(pipe);
5884 if (pipe == 1)
5922 I915_WRITE(TRANSDATA_M1(pipe), 0);
5923 I915_WRITE(TRANSDATA_N1(pipe), 0);
5924 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5925 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5975 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5991 int pipe = intel_crtc->pipe;
5994 drm_vblank_pre_modeset(dev, pipe);
5998 drm_vblank_post_modeset(dev, pipe);
6093 int pipe = to_intel_crtc(crtc)->pipe;
6096 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6097 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6098 int aud_config = HSW_AUD_CFG(pipe);
6107 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6111 intel_wait_for_vblank(dev, pipe);
6116 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6128 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6130 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6181 int pipe = to_intel_crtc(crtc)->pipe;
6184 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6185 aud_config = IBX_AUD_CFG(pipe);
6186 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6189 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6190 aud_config = CPT_AUD_CFG(pipe);
6191 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6195 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6274 int palreg = PALETTE(intel_crtc->pipe);
6283 palreg = LGC_PALETTE(intel_crtc->pipe);
6328 int pipe = intel_crtc->pipe;
6332 uint32_t cntl = I915_READ(CURCNTR(pipe));
6336 cntl |= pipe << 28; /* Connect to correct pipe */
6341 I915_WRITE(CURCNTR(pipe), cntl);
6346 I915_WRITE(CURBASE(pipe), base);
6354 int pipe = intel_crtc->pipe;
6358 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6366 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6371 I915_WRITE(CURBASE_IVB(pipe), base);
6381 int pipe = intel_crtc->pipe;
6422 I915_WRITE(CURPOS_IVB(pipe), pos);
6425 I915_WRITE(CURPOS(pipe), pos);
6495 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6585 * Get a pipe with a simple mode set on it for doing load-based monitor
6588 * It will be up to the load-detect code to adjust the pipe as appropriate for
6589 * its requirements. The pipe will be connected to no other encoders.
6591 * Currently this code will only succeed if there is a pipe with no encoders
6593 * some outputs to free up a pipe for its use.
6598 /* VESA 640x480x72Hz mode to set on the pipe */
6751 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6787 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6794 intel_wait_for_vblank(dev, intel_crtc->pipe);
6827 /* Returns the clock of the currently programmed mode of the given pipe. */
6832 int pipe = intel_crtc->pipe;
6833 u32 dpll = I915_READ(DPLL(pipe));
6838 fp = I915_READ(FP0(pipe));
6840 fp = I915_READ(FP1(pipe));
6877 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6914 /** Returns the currently programmed mode of the given pipe. */
6951 int pipe = intel_crtc->pipe;
6952 int dpll_reg = DPLL(pipe);
6965 assert_panel_unlocked(dev_priv, pipe);
6969 intel_wait_for_vblank(dev, pipe);
6994 int pipe = intel_crtc->pipe;
6995 int dpll_reg = DPLL(pipe);
7000 assert_panel_unlocked(dev_priv, pipe);
7005 intel_wait_for_vblank(dev, pipe);
7122 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7124 drm_vblank_put(dev, intel_crtc->pipe);
7140 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7298 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7342 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7345 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7456 ret = drm_vblank_get(dev, intel_crtc->pipe);
7465 drm_vblank_put(dev, intel_crtc->pipe);
7521 drm_vblank_put(dev, intel_crtc->pipe);
7605 * This function copies the stage display pipe configuration to the real one.
7668 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7693 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7698 1 << connector->new_encoder->new_crtc->pipe;
7709 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7713 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7732 *disable_pipes |= 1 << intel_crtc->pipe;
7739 *prepare_pipes |= 1 << intel_crtc->pipe;
7742 * For simplicity do a full modeset on any pipe where the output routing
7758 *modeset_pipes &= 1 << intel_crtc->pipe;
7759 *prepare_pipes &= 1 << intel_crtc->pipe;
7788 if (prepare_pipes & (1 << intel_crtc->pipe))
7806 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7826 if (mask & (1 <<(intel_crtc)->pipe)) \
7849 enum pipe pipe, tracked_pipe;
7879 active = encoder->get_hw_state(encoder, &pipe);
7888 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7889 WARN(active && pipe != tracked_pipe,
7890 "active encoder's pipe doesn't match"
7892 tracked_pipe, pipe);
7922 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7940 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7991 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8346 static void intel_crtc_init(struct drm_device *dev, int pipe)
8366 intel_crtc->pipe = pipe;
8367 intel_crtc->plane = pipe;
8368 intel_crtc->cpu_transcoder = pipe;
8371 intel_crtc->plane = !pipe;
8374 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8377 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8403 pipe_from_crtc_id->pipe = crtc->pipe;
8821 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8830 DRM_INFO("applying pipe a force quirk\n");
8900 /* HP Mini needs pipe A force quirk (LP: #322104) */
8903 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8906 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8909 /* 830/845 need to leave pipe A & dpll A up */
9031 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9064 /* We can't just switch on the pipe A, we need to set things up with a
9065 * proper mode and output configuration. As a gross hack, enable pipe A
9066 * by enabling the load detect pipe once. */
9098 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9114 /* We need to sanitize the plane -> pipe mapping first because this will
9116 * that gen4+ has a fixed plane -> pipe mapping. */
9146 crtc->pipe == PIPE_A && !crtc->active) {
9147 /* BIOS forgot to enable pipe A, this mostly happens after
9148 * resume. Force-enable the pipe to fix this, the update_dpms
9149 * call below we restore the pipe to the right state, but leave
9154 /* Adjust the state of the output pipe according to whether we
9162 * functions or because the pipe is force-enabled due to the
9163 * pipe A quirk. */
9191 * encoder is active and trying to read from a pipe) and the
9192 * pipe itself being active. */
9197 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9201 /* Connector is active, but has no active pipe. This is
9211 /* Inconsistent output/port/pipe state happens presumably due to
9251 enum pipe pipe;
9264 pipe = PIPE_A;
9267 pipe = PIPE_B;
9270 pipe = PIPE_C;
9274 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9278 pipe_name(pipe));
9282 for_each_pipe(pipe) {
9283 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9303 pipe = 0;
9305 if (encoder->get_hw_state(encoder, &pipe)) {
9307 dev_priv->pipe_to_crtc_mapping[pipe];
9313 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9317 pipe);
9342 for_each_pipe(pipe) {
9343 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9348 for_each_pipe(pipe) {
9349 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9476 } pipe[I915_MAX_PIPES];
9518 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9519 error->pipe[i].source = I915_READ(PIPESRC(i));
9520 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9521 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9522 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9523 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9524 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9525 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9542 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9543 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9544 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9545 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9546 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9547 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9548 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9549 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);