drm2/i915/intel_ddi.c

764 	uint32_t val;
771 			val = I915_READ(SPLL_CTL);
772 			WARN_ON(!(val & SPLL_PLL_ENABLE));
773 			I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
781 			val = I915_READ(WRPLL_CTL1);
782 			WARN_ON(!(val & WRPLL_PLL_ENABLE));
783 			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
791 			val = I915_READ(WRPLL_CTL2);
792 			WARN_ON(!(val & WRPLL_PLL_ENABLE));
793 			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
838 	uint32_t reg, val;
891 		val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
907 		val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
914 	I915_WRITE(reg, val);
1056 	uint32_t val = I915_READ(reg);
1058 	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1059 	val |= TRANS_DDI_PORT_NONE;
1060 	I915_WRITE(reg, val);
1266 	uint32_t val;
1269 	val = I915_READ(DDI_BUF_CTL(port));
1270 	if (val & DDI_BUF_CTL_ENABLE) {
1271 		val &= ~DDI_BUF_CTL_ENABLE;
1272 		I915_WRITE(DDI_BUF_CTL(port), val);
1276 	val = I915_READ(DP_TP_CTL(port));
1277 	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1278 	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1279 	I915_WRITE(DP_TP_CTL(port), val);
1346 	uint32_t val = I915_READ(LCPLL_CTL);
1356 	if (val & LCPLL_CD_SOURCE_FCLK)
1359 	if (val & LCPLL_PLL_DISABLE)
1370 	uint32_t val;
1373 		val = I915_READ(DDI_BUF_CTL(port));
1374 		if (val & DDI_BUF_CTL_ENABLE) {
1375 			val &= ~DDI_BUF_CTL_ENABLE;
1376 			I915_WRITE(DDI_BUF_CTL(port), val);
1380 		val = I915_READ(DP_TP_CTL(port));
1381 		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1382 		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1383 		I915_WRITE(DP_TP_CTL(port), val);
1390 	val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1393 		val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1394 	I915_WRITE(DP_TP_CTL(port), val);
1408 	uint32_t val;
1412 	val = I915_READ(_FDI_RXA_CTL);
1413 	val &= ~FDI_RX_ENABLE;
1414 	I915_WRITE(_FDI_RXA_CTL, val);
1416 	val = I915_READ(_FDI_RXA_MISC);
1417 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1418 	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1419 	I915_WRITE(_FDI_RXA_MISC, val);
1421 	val = I915_READ(_FDI_RXA_CTL);
1422 	val &= ~FDI_PCDCLK;
1423 	I915_WRITE(_FDI_RXA_CTL, val);
1425 	val = I915_READ(_FDI_RXA_CTL);
1426 	val &= ~FDI_RX_PLL_ENABLE;
1427 	I915_WRITE(_FDI_RXA_CTL, val);