drm2/i915/intel_bios.c

203 parse_lfp_panel_data(struct drm_i915_private *dev_priv,
218 	dev_priv->lvds_dither = lvds_options->pixel_dither;
232 	dev_priv->lvds_vbt = 1;
244 	dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
266 		dev_priv->lvds_downclock_avail = 1;
267 		dev_priv->lvds_downclock = downclock * 10;
280 			dev_priv->bios_lvds_val = fp_timing->lvds_reg_val;
282 				      dev_priv->bios_lvds_val);
289 parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
322 	dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;
343 parse_general_features(struct drm_i915_private *dev_priv,
346 	struct drm_device *dev = dev_priv->dev;
351 		dev_priv->int_tv_support = general->int_tv_support;
352 		dev_priv->int_crt_support = general->int_crt_support;
353 		dev_priv->lvds_use_ssc = general->enable_ssc;
354 		dev_priv->lvds_ssc_freq =
356 		dev_priv->display_clock_mode = general->display_clock_mode;
357 		dev_priv->fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
359 			      dev_priv->int_tv_support,
360 			      dev_priv->int_crt_support,
361 			      dev_priv->lvds_use_ssc,
362 			      dev_priv->lvds_ssc_freq,
363 			      dev_priv->display_clock_mode,
364 			      dev_priv->fdi_rx_polarity_inverted);
369 parse_general_definitions(struct drm_i915_private *dev_priv,
381 				dev_priv->crt_ddc_pin = bus_pin;
390 parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
445 		p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]);
480 parse_driver_features(struct drm_i915_private *dev_priv,
483 	struct drm_device *dev = dev_priv->dev;
492 		dev_priv->edp.support = 1;
495 		dev_priv->render_reclock_avail = true;
499 parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
507 		if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support)
514 		dev_priv->edp.bpp = 18;
517 		dev_priv->edp.bpp = 24;
520 		dev_priv->edp.bpp = 30;
528 	dev_priv->edp.pps = *edp_pps;
530 	dev_priv->edp.rate = edp_link_params->rate ? DP_LINK_BW_2_7 :
534 		dev_priv->edp.lanes = 1;
537 		dev_priv->edp.lanes = 2;
541 		dev_priv->edp.lanes = 4;
546 		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
549 		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
552 		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
555 		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
560 		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_400;
563 		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_600;
566 		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_800;
569 		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_1200;
575 parse_device_mapping(struct drm_i915_private *dev_priv,
617 	dev_priv->child_dev = malloc(count * sizeof(*p_child), DRM_MEM_KMS, M_WAITOK | M_ZERO);
618 	if (!dev_priv->child_dev) {
623 	dev_priv->child_dev_num = count;
631 		child_dev_ptr = dev_priv->child_dev + count;
640 init_vbt_defaults(struct drm_i915_private *dev_priv)
642 	struct drm_device *dev = dev_priv->dev;
644 	dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;
647 	dev_priv->lvds_dither = 1;
648 	dev_priv->lvds_vbt = 0;
651 	dev_priv->sdvo_lvds_vbt_mode = NULL;
654 	dev_priv->int_tv_support = 1;
655 	dev_priv->int_crt_support = 1;
658 	dev_priv->lvds_use_ssc = 1;
659 	dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
660 	DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
695 	struct drm_i915_private *dev_priv = dev->dev_private;
700 	init_vbt_defaults(dev_priv);
703 	if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt) {
704 		struct vbt_header *vbt = dev_priv->opregion.vbt;
710 			dev_priv->opregion.vbt = NULL;
740 	parse_general_features(dev_priv, bdb);
741 	parse_general_definitions(dev_priv, bdb);
742 	parse_lfp_panel_data(dev_priv, bdb);
743 	parse_sdvo_panel_data(dev_priv, bdb);
744 	parse_sdvo_device_mapping(dev_priv, bdb);
745 	parse_device_mapping(dev_priv, bdb);
746 	parse_driver_features(dev_priv, bdb);
747 	parse_edp(dev_priv, bdb);
763 	struct drm_i915_private *dev_priv = dev->dev_private;
765 	free(dev_priv->lfp_lvds_vbt_mode, DRM_MEM_KMS);
766 	free(dev_priv->sdvo_lvds_vbt_mode, DRM_MEM_KMS);
767 	free(dev_priv->child_dev, DRM_MEM_KMS);
769 	dev_priv->lfp_lvds_vbt_mode = NULL;
770 	dev_priv->sdvo_lvds_vbt_mode = NULL;
771 	dev_priv->child_dev = NULL;
779 	struct drm_i915_private *dev_priv = dev->dev_private;