Lines Matching defs:dev_priv
37 struct drm_i915_private *dev_priv = dev->dev_private;
54 struct drm_i915_private *dev_priv = dev->dev_private;
66 array = dev_priv->regfile.save_palette_a;
68 array = dev_priv->regfile.save_palette_b;
76 struct drm_i915_private *dev_priv = dev->dev_private;
88 array = dev_priv->regfile.save_palette_a;
90 array = dev_priv->regfile.save_palette_b;
98 struct drm_i915_private *dev_priv = dev->dev_private;
106 struct drm_i915_private *dev_priv = dev->dev_private;
115 struct drm_i915_private *dev_priv = dev->dev_private;
124 struct drm_i915_private *dev_priv = dev->dev_private;
132 struct drm_i915_private *dev_priv = dev->dev_private;
137 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
140 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
141 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
156 dev_priv->regfile.saveCR[i] =
159 dev_priv->regfile.saveCR[0x11] &= ~0x80;
163 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
165 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
167 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
172 dev_priv->regfile.saveGR[i] =
175 dev_priv->regfile.saveGR[0x10] =
177 dev_priv->regfile.saveGR[0x11] =
179 dev_priv->regfile.saveGR[0x18] =
184 dev_priv->regfile.saveSR[i] =
190 struct drm_i915_private *dev_priv = dev->dev_private;
195 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
196 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
209 dev_priv->regfile.saveSR[i]);
213 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
215 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
220 dev_priv->regfile.saveGR[i]);
223 dev_priv->regfile.saveGR[0x10]);
225 dev_priv->regfile.saveGR[0x11]);
227 dev_priv->regfile.saveGR[0x18]);
232 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
234 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
238 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
243 struct drm_i915_private *dev_priv = dev->dev_private;
250 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
251 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
252 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
253 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
254 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
255 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
257 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
260 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
261 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
265 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
266 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
268 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
269 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
270 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
272 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
273 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
274 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
277 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
278 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
279 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
280 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
281 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
282 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
283 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
285 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
288 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
289 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
290 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
291 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
293 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
294 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
296 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
297 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
298 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
300 dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
301 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
302 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
303 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
304 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
305 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
306 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
309 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
310 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
311 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
312 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
313 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
315 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
316 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
319 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
322 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
323 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
325 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
326 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
327 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
329 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
330 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
331 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
334 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
335 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
336 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
337 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
338 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
339 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
340 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
342 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
345 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
346 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
347 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
348 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
350 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
351 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
353 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
354 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
355 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
357 dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
358 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
359 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
360 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
361 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
362 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
363 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
366 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
367 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
368 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
369 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
370 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
372 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
373 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
376 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
383 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
388 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
393 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
396 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
402 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
404 dev_priv->regfile.saveADPA = I915_READ(ADPA);
411 struct drm_i915_private *dev_priv = dev->dev_private;
424 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
429 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
435 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
437 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
459 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
460 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
465 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
466 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
471 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
472 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
474 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
478 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
484 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
485 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
486 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
487 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
488 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
489 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
491 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
494 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
495 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
496 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
497 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
499 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
500 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
502 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
503 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
504 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
506 I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
507 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
508 I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
509 I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
510 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
511 I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
512 I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
516 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
517 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
518 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
519 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
520 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
522 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
523 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
526 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
530 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
534 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
535 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
540 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
541 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
543 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
547 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
553 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
554 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
555 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
556 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
557 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
558 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
560 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
563 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
564 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
565 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
566 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
568 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
569 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
571 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
572 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
573 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
575 I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
576 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
577 I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
578 I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
579 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
580 I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
581 I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
585 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
586 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
587 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
588 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
589 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
591 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
592 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
595 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
599 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
603 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
604 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
605 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
606 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
607 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
608 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
610 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
614 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
616 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
623 struct drm_i915_private *dev_priv = dev->dev_private;
626 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
634 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
635 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
636 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
637 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
638 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
639 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
641 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
642 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
643 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
644 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
646 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
648 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
652 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
655 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
656 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
657 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
659 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
660 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
661 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
667 dev_priv->regfile.saveDP_B = I915_READ(DP_B);
668 dev_priv->regfile.saveDP_C = I915_READ(DP_C);
669 dev_priv->regfile.saveDP_D = I915_READ(DP_D);
670 dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
671 dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
672 dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
673 dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
674 dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
675 dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
676 dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
677 dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
685 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
687 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
689 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
690 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
691 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
692 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
697 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
698 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
699 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
701 dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
703 dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
710 struct drm_i915_private *dev_priv = dev->dev_private;
713 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
718 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
719 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
720 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
721 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
722 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
723 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
724 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
725 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
735 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
738 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
740 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
743 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
746 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
747 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
751 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
752 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
753 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
754 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
755 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
756 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
758 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
760 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
761 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
762 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
763 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
764 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
765 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
766 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
772 I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
773 I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
774 I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
783 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
785 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
787 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
788 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
789 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
790 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
795 I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
797 I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
799 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
800 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
801 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
810 struct drm_i915_private *dev_priv = dev->dev_private;
813 pci_read_config_byte(dev->dev, LBB, &dev_priv->regfile.saveLBB);
822 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
823 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
824 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
825 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
826 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
827 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
828 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
830 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
832 dev_priv->regfile.saveIER = I915_READ(IER);
833 dev_priv->regfile.saveIMR = I915_READ(IMR);
840 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
843 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
847 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
848 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
851 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
860 struct drm_i915_private *dev_priv = dev->dev_private;
863 pci_write_config_byte(dev->dev, LBB, dev_priv->regfile.saveLBB);
872 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
873 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
874 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
875 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
876 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
877 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
878 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
880 I915_WRITE(IER, dev_priv->regfile.saveIER);
881 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
886 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
889 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
892 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
893 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
896 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);