drm2/i915/i915_irq.c

65 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
67 	if ((dev_priv->pipestat[pipe] & mask) != mask) {
68 		u32 reg = PIPESTAT(pipe);
70 		dev_priv->pipestat[pipe] |= mask;
72 		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
78 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
80 	if ((dev_priv->pipestat[pipe] & mask) != 0) {
81 		u32 reg = PIPESTAT(pipe);
83 		dev_priv->pipestat[pipe] &= ~mask;
84 		I915_WRITE(reg, dev_priv->pipestat[pipe]);
116  * i915_pipe_enabled - check if a pipe is enabled
118  * @pipe: pipe to check
120  * Reading certain registers when the pipe is disabled can hang the chip.
121  * Use this routine to make sure the PLL is running and the pipe is active
125 i915_pipe_enabled(struct drm_device *dev, int pipe)
129 								      pipe);
135  * we use as a pipe index
137 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
144 	if (!i915_pipe_enabled(dev, pipe)) {
146 				"pipe %c\n", pipe_name(pipe));
150 	high_frame = PIPEFRAME(pipe);
151 	low_frame = PIPEFRAMEPIXEL(pipe);
169 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
172 	int reg = PIPE_FRMCOUNT_GM45(pipe);
174 	if (!i915_pipe_enabled(dev, pipe)) {
176 				 "pipe %c\n", pipe_name(pipe));
183 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
192 								      pipe);
194 	if (!i915_pipe_enabled(dev, pipe)) {
196 				 "pipe %c\n", pipe_name(pipe));
207 		position = I915_READ(PIPEDSL(pipe));
219 		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
251 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
259 	if (pipe < 0 || pipe >= dev_priv->num_pipe) {
260 		DRM_ERROR("Invalid crtc %d\n", pipe);
265 	crtc = intel_get_crtc_for_pipe(dev, pipe);
267 		DRM_ERROR("Invalid crtc %d\n", pipe);
272 		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
277 	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
534 	int pipe;
551 		for_each_pipe(pipe) {
552 			int reg = PIPESTAT(pipe);
553 			pipe_stats[pipe] = I915_READ(reg);
558 			if (pipe_stats[pipe] & 0x8000ffff) {
559 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
560 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
561 							 pipe_name(pipe));
562 				I915_WRITE(reg, pipe_stats[pipe]);
567 		for_each_pipe(pipe) {
568 			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
569 				drm_handle_vblank(dev, pipe);
571 			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
572 				intel_prepare_page_flip(dev, pipe);
573 				intel_finish_page_flip(dev, pipe);
591 		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
609 	int pipe;
632 		for_each_pipe(pipe)
633 			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
634 					 pipe_name(pipe),
635 					 I915_READ(FDI_RX_IIR(pipe)));
652 	int pipe;
675 		for_each_pipe(pipe)
676 			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
677 					 pipe_name(pipe),
678 					 I915_READ(FDI_RX_IIR(pipe)));
1225 	int i, pipe;
1233 	/* Account for pipe specific data like PIPE*STAT */
1267 	for_each_pipe(pipe)
1268 		error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1356 	int pipe, i;
1399 		for_each_pipe(pipe)
1400 			pr_err("pipe %c stat: 0x%08x\n",
1401 			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1476 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1479 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1522  * we use as a pipe index
1524 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1528 	if (!i915_pipe_enabled(dev, pipe))
1533 		i915_enable_pipestat(dev_priv, pipe,
1536 		i915_enable_pipestat(dev_priv, pipe,
1543 	CTR1(KTR_DRM, "i915_enable_vblank %d", pipe);
1548 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1552 	if (!i915_pipe_enabled(dev, pipe))
1556 	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1559 	CTR1(KTR_DRM, "ironlake_enable_vblank %d", pipe);
1564 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1568 	if (!i915_pipe_enabled(dev, pipe))
1573 				    DE_PIPEA_VBLANK_IVB << (5 * pipe));
1575 	CTR1(KTR_DRM, "ivybridge_enable_vblank %d", pipe);
1580 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1585 	if (!i915_pipe_enabled(dev, pipe))
1590 	if (pipe == 0)
1595 	i915_enable_pipestat(dev_priv, pipe,
1603  * we use as a pipe index
1605 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1613 	i915_disable_pipestat(dev_priv, pipe,
1617 	CTR1(KTR_DRM, "i915_disable_vblank %d", pipe);
1620 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1625 	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1628 	CTR1(KTR_DRM, "ironlake_disable_vblank %d", pipe);
1631 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1637 				     DE_PIPEA_VBLANK_IVB << (pipe * 5));
1639 	CTR1(KTR_DRM, "ivybridge_disable_vblank %d", pipe);
1642 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1648 	i915_disable_pipestat(dev_priv, pipe,
1651 	if (pipe == 0)
1657 	CTR2(KTR_DRM, "%s %d", __func__, pipe);
1815 	int pipe;
1836 	for_each_pipe(pipe)
1837 		I915_WRITE(PIPESTAT(pipe), 0xffff);
2066 	int pipe;
2071 	for_each_pipe(pipe)
2072 		I915_WRITE(PIPESTAT(pipe), 0xffff);
2077 	for_each_pipe(pipe)
2078 		I915_WRITE(PIPESTAT(pipe), 0xffff);
2110 	int pipe;
2114 	for_each_pipe(pipe)
2115 		I915_WRITE(PIPESTAT(pipe), 0);
2157 	int pipe;
2178 		for_each_pipe(pipe) {
2179 			int reg = PIPESTAT(pipe);
2180 			pipe_stats[pipe] = I915_READ(reg);
2185 			if (pipe_stats[pipe] & 0x8000ffff) {
2186 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2187 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
2188 							 pipe_name(pipe));
2189 				I915_WRITE(reg, pipe_stats[pipe]);
2228 	int pipe;
2230 	for_each_pipe(pipe) {
2232 		I915_WRITE(PIPESTAT(pipe), 0);
2233 		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2243 	int pipe;
2253 	for_each_pipe(pipe)
2254 		I915_WRITE(PIPESTAT(pipe), 0);
2337 	int pipe;
2355 		for_each_pipe(pipe) {
2356 			int reg = PIPESTAT(pipe);
2357 			pipe_stats[pipe] = I915_READ(reg);
2360 			if (pipe_stats[pipe] & 0x8000ffff) {
2361 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2362 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
2363 							 pipe_name(pipe));
2364 				I915_WRITE(reg, pipe_stats[pipe]);
2394 		for_each_pipe(pipe) {
2395 			int plane = pipe;
2398 			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2399 			    drm_handle_vblank(dev, pipe)) {
2402 					intel_finish_page_flip(dev, pipe);
2407 			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2438 	int pipe;
2446 	for_each_pipe(pipe) {
2448 		I915_WRITE(PIPESTAT(pipe), 0);
2449 		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2460 	int pipe;
2468 	for_each_pipe(pipe)
2469 		I915_WRITE(PIPESTAT(pipe), 0);
2566 	int pipe;
2586 		for_each_pipe(pipe) {
2587 			int reg = PIPESTAT(pipe);
2588 			pipe_stats[pipe] = I915_READ(reg);
2593 			if (pipe_stats[pipe] & 0x8000ffff) {
2594 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2595 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
2596 							 pipe_name(pipe));
2597 				I915_WRITE(reg, pipe_stats[pipe]);
2634 		for_each_pipe(pipe) {
2635 			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2636 			    drm_handle_vblank(dev, pipe)) {
2637 				i915_pageflip_stall_check(dev, pipe);
2638 				intel_finish_page_flip(dev, pipe);
2641 			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2673 	int pipe;
2682 	for_each_pipe(pipe)
2683 		I915_WRITE(PIPESTAT(pipe), 0);
2687 	for_each_pipe(pipe)
2688 		I915_WRITE(PIPESTAT(pipe),
2689 			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);