Lines Matching defs:pm_iir
368 u32 pm_iir, pm_imr;
372 pm_iir = dev_priv->rps.pm_iir;
373 dev_priv->rps.pm_iir = 0;
378 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
383 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
507 u32 pm_iir)
514 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
521 dev_priv->rps.pm_iir |= pm_iir;
522 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
533 u32 iir, gt_iir, pm_iir;
543 pm_iir = I915_READ(GEN6_PMIIR);
545 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
594 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
595 gen6_queue_rps_work(dev_priv, pm_iir);
598 I915_WRITE(GEN6_PMIIR, pm_iir);
685 u32 de_iir, gt_iir, de_ier, pm_iir;
727 pm_iir = I915_READ(GEN6_PMIIR);
728 if (pm_iir) {
729 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
730 gen6_queue_rps_work(dev_priv, pm_iir);
731 I915_WRITE(GEN6_PMIIR, pm_iir);
738 gt_iir, pm_iir);
755 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
767 pm_iir = I915_READ(GEN6_PMIIR);
770 gt_iir, pch_iir, pm_iir);
773 (!IS_GEN6(dev) || pm_iir == 0))
811 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
812 gen6_queue_rps_work(dev_priv, pm_iir);
818 I915_WRITE(GEN6_PMIIR, pm_iir);