Lines Matching refs:dev_priv
44 intel_ring_begin(LP_RING(dev_priv), (n))
47 intel_ring_emit(LP_RING(dev_priv), x)
50 intel_ring_advance(LP_RING(dev_priv))
64 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
66 if (I915_NEED_GFX_HWS(dev_priv->dev))
67 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
69 return intel_read_status_page(LP_RING(dev_priv), reg);
72 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
73 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
78 drm_i915_private_t *dev_priv = dev->dev_private;
85 READ_BREADCRUMB(dev_priv);
91 drm_i915_private_t *dev_priv = dev->dev_private;
94 addr = dev_priv->status_page_dmah->busaddr;
96 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
106 drm_i915_private_t *dev_priv = dev->dev_private;
107 struct intel_ring_buffer *ring = LP_RING(dev_priv);
109 if (dev_priv->status_page_dmah) {
110 drm_pci_free(dev, dev_priv->status_page_dmah);
111 dev_priv->status_page_dmah = NULL;
116 pmap_unmapdev((vm_offset_t)dev_priv->dri1.gfx_hws_cpu_addr,
126 drm_i915_private_t *dev_priv = dev->dev_private;
128 struct intel_ring_buffer *ring = LP_RING(dev_priv);
153 drm_i915_private_t *dev_priv = dev->dev_private;
165 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
177 drm_i915_private_t *dev_priv = dev->dev_private;
190 if (LP_RING(dev_priv)->obj != NULL) {
206 dev_priv->dri1.cpp = init->cpp;
207 dev_priv->dri1.back_offset = init->back_offset;
208 dev_priv->dri1.front_offset = init->front_offset;
209 dev_priv->dri1.current_page = 0;
215 dev_priv->dri1.allow_batchbuffer = 1;
222 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
223 struct intel_ring_buffer *ring = LP_RING(dev_priv);
346 drm_i915_private_t *dev_priv = dev->dev_private;
349 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
378 struct drm_i915_private *dev_priv = dev->dev_private;
420 drm_i915_private_t *dev_priv = dev->dev_private;
423 dev_priv->dri1.counter++;
424 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
425 dev_priv->dri1.counter = 0;
427 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
432 OUT_RING(dev_priv->dri1.counter);
476 struct drm_i915_private *dev_priv = dev->dev_private;
536 drm_i915_private_t *dev_priv = dev->dev_private;
546 dev_priv->dri1.current_page,
560 if (dev_priv->dri1.current_page == 0) {
561 OUT_RING(dev_priv->dri1.back_offset);
562 dev_priv->dri1.current_page = 1;
564 OUT_RING(dev_priv->dri1.front_offset);
565 dev_priv->dri1.current_page = 0;
574 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
579 OUT_RING(dev_priv->dri1.counter);
584 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
614 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
625 if (!dev_priv->dri1.allow_batchbuffer) {
659 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
670 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
726 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
738 drm_i915_private_t *dev_priv = dev->dev_private;
745 dev_priv->dri1.counter++;
746 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
747 dev_priv->dri1.counter = 1;
749 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
754 OUT_RING(dev_priv->dri1.counter);
759 return dev_priv->dri1.counter;
764 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
767 struct intel_ring_buffer *ring = LP_RING(dev_priv);
770 READ_BREADCRUMB(dev_priv));
772 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
774 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
782 mtx_lock(&dev_priv->irq_lock);
783 while (ret == 0 && READ_BREADCRUMB(dev_priv) < irq_nr) {
784 ret = -msleep(&ring->irq_queue, &dev_priv->irq_lock,
789 mtx_unlock(&dev_priv->irq_lock);
791 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
796 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
807 drm_i915_private_t *dev_priv = dev->dev_private;
814 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
838 drm_i915_private_t *dev_priv = dev->dev_private;
844 if (!dev_priv) {
855 drm_i915_private_t *dev_priv = dev->dev_private;
861 if (!dev_priv) {
916 drm_i915_private_t *dev_priv = dev->dev_private;
920 if (!dev_priv) {
930 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
933 value = READ_BREADCRUMB(dev_priv);
942 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
945 value = dev_priv->overlay ? 1 : 0;
955 value = intel_ring_initialized(&dev_priv->ring[VCS]);
958 value = intel_ring_initialized(&dev_priv->ring[BCS]);
979 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1015 drm_i915_private_t *dev_priv = dev->dev_private;
1018 if (!dev_priv) {
1029 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1032 if (param->value > dev_priv->num_fence_regs ||
1036 dev_priv->fence_reg_start = param->value;
1050 drm_i915_private_t *dev_priv = dev->dev_private;
1060 if (!dev_priv) {
1072 ring = LP_RING(dev_priv);
1075 dev_priv->dri1.gfx_hws_cpu_addr =
1076 pmap_mapdev_attr(dev_priv->mm.gtt_base_addr + hws->addr, PAGE_SIZE,
1078 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1086 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1100 dev_priv->bridge_dev = pci_find_dbsf(0, 0, 0, 0);
1101 if (!dev_priv->bridge_dev) {
1119 drm_i915_private_t *dev_priv = dev->dev_private;
1125 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1126 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1139 dev_priv->mch_res_rid = 0x100;
1140 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1141 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1143 if (dev_priv->mch_res == NULL) {
1149 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1150 upper_32_bits(rman_get_start(dev_priv->mch_res)));
1152 pci_write_config_dword(dev_priv->bridge_dev, reg,
1153 lower_32_bits(rman_get_start(dev_priv->mch_res)));
1161 drm_i915_private_t *dev_priv = dev->dev_private;
1166 dev_priv->mchbar_need_disable = false;
1169 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1172 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1183 dev_priv->mchbar_need_disable = true;
1187 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1190 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1191 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1198 drm_i915_private_t *dev_priv = dev->dev_private;
1202 if (dev_priv->mchbar_need_disable) {
1204 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1206 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1208 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1210 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1214 if (dev_priv->mch_res != NULL) {
1218 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1220 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1221 dev_priv->mch_res = NULL;
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1319 TASK_INIT(&dev_priv->console_resume_work, 0, intel_console_resume,
1337 dev_priv->mm.suspended = 0;
1386 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1389 dev_priv->mm.gtt_mtrr = -1;
1401 dev_priv->mm.gtt_mtrr = drm_mtrr_add(base, size, DRM_MTRR_WC);
1402 if (dev_priv->mm.gtt_mtrr < 0) {
1409 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1412 struct pci_dev *pdev = dev_priv->dev->pdev;
1419 ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1421 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1431 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1433 const struct intel_device_info *info = dev_priv->info;
1440 dev_priv->dev->pci_device,
1459 struct drm_i915_private *dev_priv;
1477 dev_priv = malloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1479 if (dev_priv == NULL)
1482 dev->dev_private = (void *)dev_priv;
1483 dev_priv->dev = dev;
1484 dev_priv->info = info;
1486 i915_dump_device_info(dev_priv);
1499 i915_kick_out_firmware_fb(dev_priv);
1534 _DRM_REGISTERS, _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1541 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1542 dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1545 dev_priv->mm.gtt_mapping =
1546 io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1548 if (dev_priv->mm.gtt_mapping == NULL) {
1554 i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1570 dev_priv->wq = taskqueue_create("915", M_WAITOK,
1571 taskqueue_thread_enqueue, &dev_priv->wq);
1572 if (dev_priv->wq == NULL) {
1577 taskqueue_start_threads(&dev_priv->wq, 1, PWAIT, "i915 taskq");
1608 mtx_init(&dev_priv->irq_lock, "userirq", NULL, MTX_DEF);
1609 mtx_init(&dev_priv->error_lock, "915err", NULL, MTX_DEF);
1610 mtx_init(&dev_priv->rps.lock, "915rps", NULL, MTX_DEF);
1611 sx_init(&dev_priv->dpio_lock, "915dpi");
1613 sx_init(&dev_priv->rps.hw_lock, "915rpshw");
1616 dev_priv->num_pipe = 3;
1618 dev_priv->num_pipe = 2;
1620 dev_priv->num_pipe = 1;
1622 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1627 dev_priv->mm.suspended = 1;
1649 callout_init(&dev_priv->hangcheck_timer, 1);
1650 callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1654 intel_gpu_ips_init(dev_priv);
1659 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.inactive_shrinker);
1661 free_completion(&dev_priv->error_completion);
1662 mtx_destroy(&dev_priv->irq_lock);
1663 mtx_destroy(&dev_priv->error_lock);
1664 mtx_destroy(&dev_priv->rps.lock);
1665 sx_destroy(&dev_priv->dpio_lock);
1667 sx_destroy(&dev_priv->rps.hw_lock);
1674 if (dev_priv->wq != NULL) {
1675 taskqueue_free(dev_priv->wq);
1676 dev_priv->wq = NULL;
1679 if (dev_priv->mm.gtt_mtrr >= 0) {
1680 drm_mtrr_del(dev_priv->mm.gtt_mtrr,
1681 dev_priv->mm.gtt_base_addr,
1684 dev_priv->mm.gtt_mtrr = -1;
1687 io_mapping_free(dev_priv->mm.gtt_mapping);
1690 if (dev_priv->mmio_map != NULL)
1691 drm_rmmap(dev, dev_priv->mmio_map);
1696 pci_dev_put(dev_priv->bridge_dev);
1699 free(dev_priv, DRM_MEM_DRIVER);
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1713 if (dev_priv->mm.inactive_shrinker.shrink)
1714 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1727 while (taskqueue_cancel_timeout(dev_priv->wq,
1728 &dev_priv->mm.retire_work, NULL) != 0)
1729 taskqueue_drain_timeout(dev_priv->wq,
1730 &dev_priv->mm.retire_work);
1733 io_mapping_free(dev_priv->mm.gtt_mapping);
1735 if (dev_priv->mm.gtt_mtrr >= 0) {
1736 drm_mtrr_del(dev_priv->mm.gtt_mtrr,
1737 dev_priv->mm.gtt_base_addr,
1738 dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE,
1740 dev_priv->mm.gtt_mtrr = -1;
1750 while (taskqueue_cancel(dev_priv->wq,
1751 &dev_priv->console_resume_work, NULL) != 0)
1752 taskqueue_drain(dev_priv->wq,
1753 &dev_priv->console_resume_work);
1759 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1760 free(dev_priv->child_dev, DRM_MEM_DRIVER);
1761 dev_priv->child_dev = NULL;
1762 dev_priv->child_dev_num = 0;
1772 callout_stop(&dev_priv->hangcheck_timer);
1773 callout_drain(&dev_priv->hangcheck_timer);
1774 while (taskqueue_cancel(dev_priv->wq, &dev_priv->error_work, NULL) != 0)
1775 taskqueue_drain(dev_priv->wq, &dev_priv->error_work);
1785 taskqueue_drain_all(dev_priv->wq);
1794 drm_mm_takedown(&dev_priv->mm.stolen);
1810 if (dev_priv->mmio_map != NULL)
1811 drm_rmmap(dev, dev_priv->mmio_map);
1819 if (dev_priv->wq != NULL)
1820 taskqueue_free(dev_priv->wq);
1822 free_completion(&dev_priv->error_completion);
1823 mtx_destroy(&dev_priv->irq_lock);
1824 mtx_destroy(&dev_priv->error_lock);
1825 mtx_destroy(&dev_priv->rps.lock);
1826 sx_destroy(&dev_priv->dpio_lock);
1828 sx_destroy(&dev_priv->rps.hw_lock);
1831 pci_dev_put(dev_priv->bridge_dev);
1871 drm_i915_private_t *dev_priv = dev->dev_private;
1876 if (!dev_priv)