41 #define	seq_printf(m, fmt, ...)	sbuf_printf((m), (fmt), ##__VA_ARGS__)
60 	seq_printf(m, "gen: %d\n", info->gen);
61 	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
62 #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
104 	seq_printf(m, "%pK: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
118 		seq_printf(m, " (name: %d)", obj->base.name);
120 		seq_printf(m, " (pinned x %d)", obj->pin_count);
122 		seq_printf(m, " (display)");
124 		seq_printf(m, " (fence: %d)", obj->fence_reg);
126 		seq_printf(m, " (gtt offset: %08x, size: %08x)",
135 		seq_printf(m, " (%s mappable)", s);
138 		seq_printf(m, " (%s)", obj->ring->name);
155 		seq_printf(m, "Active:\n");
159 		seq_printf(m, "Inactive:\n");
169 		seq_printf(m, "   ");
171 		seq_printf(m, "\n");
178 	seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
204 	seq_printf(m, "%u objects, %zu bytes\n",
210 	seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
215 	seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
220 	seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
229 	seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
246 	seq_printf(m, "%u purgeable objects, %zu bytes\n",
248 	seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
250 	seq_printf(m, "%u fault mappable objects, %zu bytes\n",
253 	seq_printf(m, "%zu [%zu] gtt total\n",
277 		seq_printf(m, "   ");
279 		seq_printf(m, "\n");
287 	seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
305 			seq_printf(m, "No flip due on pipe %c (plane %c)\n",
309 				seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
312 				seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
316 				seq_printf(m, "Stall check enabled, ");
318 				seq_printf(m, "Stall check waiting for page flip ioctl, ");
319 			seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
324 					seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
329 					seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
353 		seq_printf(m, "%s requests:\n", ring->name);
357 			seq_printf(m, "    %d @ %d\n",
366 		seq_printf(m, "No requests\n");
375 		seq_printf(m, "Current sequence (%s): %d\n",
408 		seq_printf(m, "Display IER:\t%08x\n",
410 		seq_printf(m, "Display IIR:\t%08x\n",
412 		seq_printf(m, "Display IIR_RW:\t%08x\n",
414 		seq_printf(m, "Display IMR:\t%08x\n",
417 			seq_printf(m, "Pipe %c stat:\t%08x\n",
421 		seq_printf(m, "Master IER:\t%08x\n",
424 		seq_printf(m, "Render IER:\t%08x\n",
426 		seq_printf(m, "Render IIR:\t%08x\n",
428 		seq_printf(m, "Render IMR:\t%08x\n",
431 		seq_printf(m, "PM IER:\t\t%08x\n",
433 		seq_printf(m, "PM IIR:\t\t%08x\n",
435 		seq_printf(m, "PM IMR:\t\t%08x\n",
438 		seq_printf(m, "Port hotplug:\t%08x\n",
440 		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
442 		seq_printf(m, "DPINVGTT:\t%08x\n",
446 		seq_printf(m, "Interrupt enable:    %08x\n",
448 		seq_printf(m, "Interrupt identity:  %08x\n",
450 		seq_printf(m, "Interrupt mask:      %08x\n",
453 			seq_printf(m, "Pipe %c stat:         %08x\n",
457 		seq_printf(m, "North Display Interrupt enable:		%08x\n",
459 		seq_printf(m, "North Display Interrupt identity:	%08x\n",
461 		seq_printf(m, "North Display Interrupt mask:		%08x\n",
463 		seq_printf(m, "South Display Interrupt enable:		%08x\n",
465 		seq_printf(m, "South Display Interrupt identity:	%08x\n",
467 		seq_printf(m, "South Display Interrupt mask:		%08x\n",
469 		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
471 		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
473 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
476 	seq_printf(m, "Interrupts received: %d\n",
480 			seq_printf(m,
499 	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
500 	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
504 		seq_printf(m, "Fence %d, pin count = %d, object = ",
507 			seq_printf(m, "unused");
510 		seq_printf(m, "\n");
530 		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
583 	seq_printf(m, "%s [%d]:\n", name, count);
586 		seq_printf(m, "  %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
601 			seq_printf(m, " (name: %d)", err->name);
603 			seq_printf(m, " (fence: %d)", err->fence_reg);
605 		seq_printf(m, "\n");
616 	seq_printf(m, "%s command stream:\n", ring_str(ring));
617 	seq_printf(m, "  HEAD: 0x%08x\n", error->head[ring]);
618 	seq_printf(m, "  TAIL: 0x%08x\n", error->tail[ring]);
619 	seq_printf(m, "  CTL: 0x%08x\n", error->ctl[ring]);
620 	seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd[ring]);
621 	seq_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
622 	seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
623 	seq_printf(m, "  INSTDONE: 0x%08x\n", error->instdone[ring]);
625 		seq_printf(m, "  BBADDR: 0x%08jx\n", error->bbaddr);
628 		seq_printf(m, "  INSTPS: 0x%08x\n", error->instps[ring]);
629 	seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm[ring]);
630 	seq_printf(m, "  FADDR: 0x%08x\n", error->faddr[ring]);
632 		seq_printf(m, "  RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
633 		seq_printf(m, "  FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
634 		seq_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
637 		seq_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
641 	seq_printf(m, "  seqno: 0x%08x\n", error->seqno[ring]);
642 	seq_printf(m, "  waiting: %s\n", yesno(error->waiting[ring]));
643 	seq_printf(m, "  ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
644 	seq_printf(m, "  ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
662 		seq_printf(m, "no error state collected\n");
666 	seq_printf(m, "Time: %jd s %jd us\n", (intmax_t)error->time.tv_sec,
668 	seq_printf(m, "Kernel: %s\n", version);
669 	seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
670 	seq_printf(m, "EIR: 0x%08x\n", error->eir);
671 	seq_printf(m, "IER: 0x%08x\n", error->ier);
672 	seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
673 	seq_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
674 	seq_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
675 	seq_printf(m, "CCID: 0x%08x\n", error->ccid);
678 		seq_printf(m, "  fence[%d] = %08jx\n", i,
682 		seq_printf(m, "  INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
685 		seq_printf(m, "ERROR: 0x%08x\n", error->error);
686 		seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
690 		seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
709 			seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
715 					seq_printf(m, "%08x :  %08x\n", offset, obj->pages[page][elt]);
722 			seq_printf(m, "%s --- %d requests\n",
726 				seq_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
734 			seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
740 					seq_printf(m, "%08x :  %08x\n",
786 	seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
799 		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
800 		seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
801 		seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
803 		seq_printf(m, "Current P-state: %d\n",
835 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
836 		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
837 		seq_printf(m, "Render p-state ratio: %d\n",
839 		seq_printf(m, "Render p-state VID: %d\n",
841 		seq_printf(m, "Render p-state limit: %d\n",
843 		seq_printf(m, "CAGF: %dMHz\n", cagf);
844 		seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
846 		seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
848 		seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
850 		seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
852 		seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
854 		seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
858 		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
862 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
866 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
869 		seq_printf(m, "no P-state info available\n");
886 		seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
911 		seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
934 	seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
936 	seq_printf(m, "Boost freq: %d\n",
939 	seq_printf(m, "HW control enabled: %s\n",
941 	seq_printf(m, "SW control enabled: %s\n",
943 	seq_printf(m, "Gated voltage change: %s\n",
945 	seq_printf(m, "Starting frequency: P%d\n",
947 	seq_printf(m, "Max P-state: P%d\n",
949 	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
950 	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
951 	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
952 	seq_printf(m, "Render standby enabled: %s\n",
954 	seq_printf(m, "Current RS state: ");
957 		seq_printf(m, "on\n");
960 		seq_printf(m, "RC1\n");
963 		seq_printf(m, "RC1E\n");
966 		seq_printf(m, "RS1\n");
969 		seq_printf(m, "RS2 (RC6)\n");
972 		seq_printf(m, "RC3 (RC6+)\n");
975 		seq_printf(m, "unknown\n");
998 		seq_printf(m, "RC information inaccurate because somebody "
1004 		seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1017 	seq_printf(m, "Video Turbo Mode: %s\n",
1019 	seq_printf(m, "HW control enabled: %s\n",
1021 	seq_printf(m, "SW control enabled: %s\n",
1024 	seq_printf(m, "RC1e Enabled: %s\n",
1026 	seq_printf(m, "RC6 Enabled: %s\n",
1028 	seq_printf(m, "Deep RC6 Enabled: %s\n",
1030 	seq_printf(m, "Deepest RC6 Enabled: %s\n",
1032 	seq_printf(m, "Current RC state: ");
1036 			seq_printf(m, "Core Power Down\n");
1038 			seq_printf(m, "on\n");
1041 		seq_printf(m, "RC3\n");
1044 		seq_printf(m, "RC6\n");
1047 		seq_printf(m, "RC7\n");
1050 		seq_printf(m, "Unknown\n");
1054 	seq_printf(m, "Core Power Down: %s\n",
1058 	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1060 	seq_printf(m, "RC6 residency since boot: %u\n",
1062 	seq_printf(m, "RC6+ residency since boot: %u\n",
1064 	seq_printf(m, "RC6++ residency since boot: %u\n",
1067 	seq_printf(m, "RC6   voltage: %dmV\n",
1069 	seq_printf(m, "RC6+  voltage: %dmV\n",
1071 	seq_printf(m, "RC6++ voltage: %dmV\n",
1090 		seq_printf(m, "FBC unsupported on this chipset\n");
1095 		seq_printf(m, "FBC enabled\n");
1097 		seq_printf(m, "FBC disabled: ");
1100 			seq_printf(m, "no outputs");
1103 			seq_printf(m, "not enough stolen memory");
1106 			seq_printf(m, "mode not supported");
1109 			seq_printf(m, "mode too large");
1112 			seq_printf(m, "FBC unsupported on plane");
1115 			seq_printf(m, "scanout buffer not tiled");
1118 			seq_printf(m, "multiple pipes are enabled");
1121 			seq_printf(m, "disabled per module param (default off)");
1124 			seq_printf(m, "unknown reason");
1126 		seq_printf(m, "\n");
1145 	seq_printf(m, "self-refresh: %s\n",
1167 	seq_printf(m, "GMCH temp: %ld\n", temp);
1168 	seq_printf(m, "Chipset power: %ld\n", chipset);
1169 	seq_printf(m, "GFX power: %ld\n", gfx);
1170 	seq_printf(m, "Total power: %ld\n", chipset + gfx);
1182 		seq_printf(m, "unsupported on this chipset\n");
1188 	seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1197 		seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
1212 	seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1253 	seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1259 	seq_printf(m, "\n");
1265 		seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1271 		seq_printf(m, "\n");
1289 		seq_printf(m, "power context ");
1291 		seq_printf(m, "\n");
1295 		seq_printf(m, "render context ");
1297 		seq_printf(m, "\n");
1315 	seq_printf(m, "forcewake count = %u\n", forcewake_count);
1354 	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1356 	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1360 		seq_printf(m, "DDC = 0x%08x\n",
1362 		seq_printf(m, "C0DRB3 = 0x%04x\n",
1364 		seq_printf(m, "C1DRB3 = 0x%04x\n",
1367 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1369 		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1371 		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1373 		seq_printf(m, "TILECTL = 0x%08x\n",
1375 		seq_printf(m, "ARB_MODE = 0x%08x\n",
1377 		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1396 		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1399 		seq_printf(m, "%s\n", ring->name);
1401 			seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1402 		seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1403 		seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1404 		seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1409 		seq_printf(m, "aliasing PPGTT:\n");
1410 		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1412 	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1425 		seq_printf(m, "unsupported\n");
1433 	seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1435 	seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1437 	seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1440 	seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1442 	seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1445 	seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1447 	seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1450 	seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1452 	seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1455 	seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",

Indexes created Mon Jun 03 19:47:05 MDT 2024