dev/drm/radeon_state.c

1492 	unsigned int prim;
1500 				      drm_radeon_tcl_prim_t * prim)
1504 	int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1505 	int numverts = (int)prim->numverts;
1511 		  prim->prim,
1512 		  prim->vc_format, prim->start, prim->finish, prim->numverts);
1514 	if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1515 		DRM_ERROR("bad prim %x numverts %d\n",
1516 			  prim->prim, prim->numverts);
1532 		OUT_RING(prim->vc_format);
1533 		OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1603 				       drm_radeon_tcl_prim_t * prim)
1607 	int offset = dev_priv->gart_buffers_offset + prim->offset;
1611 	int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1612 	int count = (prim->finish - start) / sizeof(u16);
1616 		  prim->prim,
1617 		  prim->vc_format,
1618 		  prim->start, prim->finish, prim->offset, prim->numverts);
1620 	if (bad_prim_vertex_nr(prim->prim, count)) {
1621 		DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1625 	if (start >= prim->finish || (prim->start & 0x7)) {
1626 		DRM_ERROR("buffer prim %d\n", prim->prim);
1630 	dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1633 			elt_buf->offset + prim->start);
1637 	data[2] = prim->numverts;
1638 	data[3] = prim->vc_format;
1639 	data[4] = (prim->prim |
1650 					    prim->start, prim->finish);
2222 	drm_radeon_tcl_prim_t prim;
2236 	if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2237 		DRM_ERROR("buffer prim %d\n", vertex->prim);
2276 		prim.start = 0;
2277 		prim.finish = vertex->count;	/* unused */
2278 		prim.prim = vertex->prim;
2279 		prim.numverts = vertex->count;
2280 		prim.vc_format = sarea_priv->vc_format;
2282 		radeon_cp_dispatch_vertex(dev, buf, &prim);
2300 	drm_radeon_tcl_prim_t prim;
2316 	if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2317 		DRM_ERROR("buffer prim %d\n", elts->prim);
2367 	prim.start = elts->start;
2368 	prim.finish = elts->end;
2369 	prim.prim = elts->prim;
2370 	prim.offset = 0;	/* offset from start of dma buffers */
2371 	prim.numverts = RADEON_MAX_VB_VERTS;	/* duh */
2372 	prim.vc_format = sarea_priv->vc_format;
2374 	radeon_cp_dispatch_indices(dev, buf, &prim);
2546 		drm_radeon_prim_t prim;
2549 		if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim)))
2552 		if (prim.stateidx != laststate) {
2556 					       &vertex->state[prim.stateidx],
2565 			laststate = prim.stateidx;
2568 		tclprim.start = prim.start;
2569 		tclprim.finish = prim.finish;
2570 		tclprim.prim = prim.prim;
2571 		tclprim.vc_format = prim.vc_format;
2573 		if (prim.prim & RADEON_PRIM_WALK_IND) {
2574 			tclprim.offset = prim.numverts * 64;
2579 			tclprim.numverts = prim.numverts;