dev/drm/radeon_state.c

752 	x += dev_priv->sarea_priv->boxes[0].x1;
753 	y += dev_priv->sarea_priv->boxes[0].y1;
781 	if (dev_priv->sarea_priv->pfCurrentPage == 1) {
857 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
859 	int nbox = sarea_priv->nbox;
860 	struct drm_clip_rect *pbox = sarea_priv->boxes;
869 	if (sarea_priv->pfCurrentPage == 1) {
895 		sarea_priv->ctx_owner = 0;
972 		sarea_priv->ctx_owner = 0;
1219 		sarea_priv->ctx_owner = 0;
1226 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1290 		sarea_priv->ctx_owner = 0;
1297 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1333 	sarea_priv->last_clear++;
1337 	RADEON_CLEAR_AGE(sarea_priv->last_clear);
1346 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1347 	int nbox = sarea_priv->nbox;
1348 	struct drm_clip_rect *pbox = sarea_priv->boxes;
1390 		if (sarea_priv->pfCurrentPage == 0) {
1410 	sarea_priv->last_frame++;
1414 	RADEON_FRAME_AGE(sarea_priv->last_frame);
1424 	int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
1428 		  dev_priv->sarea_priv->pfCurrentPage);
1446 	OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1455 	dev_priv->sarea_priv->last_frame++;
1456 	dev_priv->sarea_priv->pfCurrentPage =
1457 		1 - dev_priv->sarea_priv->pfCurrentPage;
1461 	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1503 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1506 	int nbox = sarea_priv->nbox;
1523 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1550 	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1606 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1613 	int nbox = sarea_priv->nbox;
1647 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
2121 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2130 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2131 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2134 			       sarea_priv->nbox * sizeof(depth_boxes[0])))
2164 	if (dev_priv->sarea_priv->pfCurrentPage != 1)
2165 		dev_priv->sarea_priv->pfCurrentPage = 0;
2194 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2202 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2203 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2209 	sarea_priv->ctx_owner = 0;
2218 	drm_radeon_sarea_t *sarea_priv;
2226 	sarea_priv = dev_priv->sarea_priv;
2261 		if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2263 					      &sarea_priv->context_state,
2264 					      sarea_priv->tex_state,
2265 					      sarea_priv->dirty)) {
2270 			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2280 		prim.vc_format = sarea_priv->vc_format;
2296 	drm_radeon_sarea_t *sarea_priv;
2305 	sarea_priv = dev_priv->sarea_priv;
2350 	if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2352 				      &sarea_priv->context_state,
2353 				      sarea_priv->tex_state,
2354 				      sarea_priv->dirty)) {
2359 		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2372 	prim.vc_format = sarea_priv->vc_format;
2506 	drm_radeon_sarea_t *sarea_priv;
2515 	sarea_priv = dev_priv->sarea_priv;
2542 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2585 		if (sarea_priv->nbox == 1)
2586 			sarea_priv->nbox = 0;
3117 			if (dev_priv->sarea_priv)
3118 				dev_priv->sarea_priv->tiling_enabled = 0;
3123 			if (dev_priv->sarea_priv)
3124 				dev_priv->sarea_priv->tiling_enabled = 1;
3174 		if (dev_priv->sarea_priv &&
3175 		    dev_priv->sarea_priv->pfCurrentPage != 0)