dev/drm/radeon_irq.c

43 	drm_radeon_private_t *dev_priv = dev->dev_private;
46 		dev_priv->irq_enable_reg |= mask;
48 		dev_priv->irq_enable_reg &= ~mask;
51 		RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
56 	drm_radeon_private_t *dev_priv = dev->dev_private;
59 		dev_priv->r500_disp_irq_reg |= mask;
61 		dev_priv->r500_disp_irq_reg &= ~mask;
64 		RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
69 	drm_radeon_private_t *dev_priv = dev->dev_private;
71 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
104 	drm_radeon_private_t *dev_priv = dev->dev_private;
106 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
135 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
141 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
191 	drm_radeon_private_t *dev_priv =
197 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
203 	stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
207 	stat &= dev_priv->irq_enable_reg;
211 		DRM_WAKEUP(&dev_priv->swi_queue);
214 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
226 		switch(dev_priv->flags & RADEON_FAMILY_MASK) {
258 	drm_radeon_private_t *dev_priv = dev->dev_private;
262 	atomic_inc(&dev_priv->swi_emitted);
263 	ret = atomic_read(&dev_priv->swi_emitted);
276 	drm_radeon_private_t *dev_priv =
283 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
285 	DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
296 	drm_radeon_private_t *dev_priv = dev->dev_private;
298 	if (!dev_priv) {
308 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
325 	drm_radeon_private_t *dev_priv = dev->dev_private;
329 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
334 	if (!dev_priv) {
353 	drm_radeon_private_t *dev_priv = dev->dev_private;
356 	if (!dev_priv) {
368 	drm_radeon_private_t *dev_priv =
372 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
376 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
381 	radeon_acknowledge_irqs(dev_priv, &dummy);
386 	drm_radeon_private_t *dev_priv =
389 	atomic_set(&dev_priv->swi_emitted, 0);
390 	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
392 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
402 	drm_radeon_private_t *dev_priv =
404 	if (!dev_priv)
407 	dev_priv->irq_enabled = 0;
409 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
412 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
421 	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
423 	return dev_priv->vblank_crtc;
428 	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
433 	dev_priv->vblank_crtc = (unsigned int)value;