dev/drm/radeon_cp.c

852 	u32 temp;
860 		temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
871 		temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
877 		temp = dev_priv->gart_info.bus_addr & 0xfffff000;
878 		temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
879 		IGP_WRITE_MCIND(RS480_GART_BASE, temp);
881 		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
888 		temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
891 		radeon_write_agp_location(dev_priv, temp);
893 		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
898 			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
899 			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
908 			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
909 			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
923 	u32 temp;
967 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
968 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
970 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
971 		IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
974 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
976 		temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
977 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
978 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
980 		temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
981 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
982 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
984 		temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
985 		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
986 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
990 		temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
991 		temp &= ~RS600_ENABLE_PAGE_TABLES;
992 		IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);