Lines Matching refs:dev_priv
46 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
48 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
52 if (dev_priv->flags & RADEON_IS_AGP) {
53 val = DRM_READ32(dev_priv->ring_rptr, off);
56 dev_priv->ring_rptr->virtual) +
63 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
65 if (dev_priv->writeback_works)
66 return radeon_read_ring_rptr(dev_priv, 0);
68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
75 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
77 if (dev_priv->flags & RADEON_IS_AGP)
78 DRM_WRITE32(dev_priv->ring_rptr, off, val);
80 *(((volatile u32 *) dev_priv->ring_rptr->virtual) +
84 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
86 radeon_write_ring_rptr(dev_priv, 0, val);
89 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
91 if (dev_priv->writeback_works) {
92 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
93 return radeon_read_ring_rptr(dev_priv,
96 return radeon_read_ring_rptr(dev_priv,
99 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
106 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
111 ret = DRM_READ32(dev_priv->mmio, addr);
113 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
114 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
120 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
129 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
138 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
147 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
156 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
158 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
159 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
160 return RS690_READ_MCIND(dev_priv, addr);
161 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
162 return RS600_READ_MCIND(dev_priv, addr);
164 return RS480_READ_MCIND(dev_priv, addr);
167 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
170 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
172 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
175 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
176 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
177 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
178 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
180 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
181 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
182 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
187 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
191 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
193 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
195 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
196 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
200 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
206 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
212 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
215 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
217 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
218 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
220 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
222 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
228 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
237 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
239 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
242 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
243 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
246 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
249 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
252 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
253 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
258 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
263 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
267 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
268 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
272 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
273 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
274 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
284 drm_radeon_private_t *dev_priv = dev->dev_private;
290 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
297 static void radeon_status(drm_radeon_private_t * dev_priv)
323 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
328 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
330 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
335 for (i = 0; i < dev_priv->usec_timeout; i++) {
349 radeon_status(dev_priv);
354 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
358 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
360 for (i = 0; i < dev_priv->usec_timeout; i++) {
373 radeon_status(dev_priv);
378 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
382 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
384 ret = radeon_do_wait_for_fifo(dev_priv, 64);
388 for (i = 0; i < dev_priv->usec_timeout; i++) {
391 radeon_do_pixcache_flush(dev_priv);
402 radeon_status(dev_priv);
407 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
411 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
414 dev_priv->num_z_pipes = 2;
416 dev_priv->num_z_pipes = 1;
418 dev_priv->num_z_pipes = 1;
421 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
423 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
426 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
427 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
428 dev_priv->num_gb_pipes = 2;
431 dev_priv->num_gb_pipes = 1;
434 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
438 switch (dev_priv->num_gb_pipes) {
446 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
448 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
451 radeon_do_wait_for_idle(dev_priv);
465 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
472 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
525 radeon_do_wait_for_idle(dev_priv);
539 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
552 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
566 return radeon_do_wait_for_idle(dev_priv);
571 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
576 radeon_do_wait_for_idle(dev_priv);
578 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
580 dev_priv->cp_running = 1;
595 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
602 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
609 SET_RING_HEAD(dev_priv, cur_read_ptr);
610 dev_priv->ring.tail = cur_read_ptr;
617 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
623 dev_priv->cp_running = 0;
630 drm_radeon_private_t *dev_priv = dev->dev_private;
634 radeon_do_pixcache_flush(dev_priv);
636 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
671 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
678 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
679 radeon_init_pipes(dev_priv);
682 radeon_do_cp_reset(dev_priv);
685 dev_priv->cp_running = 0;
694 drm_radeon_private_t *dev_priv,
704 if (!dev_priv->new_memmap)
705 radeon_write_fb_location(dev_priv,
706 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
707 | (dev_priv->fb_location >> 16));
710 if (dev_priv->flags & RADEON_IS_AGP) {
711 radeon_write_agp_base(dev_priv, dev->agp->base);
713 radeon_write_agp_location(dev_priv,
714 (((dev_priv->gart_vm_start - 1 +
715 dev_priv->gart_size) & 0xffff0000) |
716 (dev_priv->gart_vm_start >> 16)));
718 ring_start = (dev_priv->cp_ring->offset
720 + dev_priv->gart_vm_start);
723 ring_start = (dev_priv->cp_ring->offset - dev->sg->vaddr +
724 dev_priv->gart_vm_start);
734 SET_RING_HEAD(dev_priv, cur_read_ptr);
735 dev_priv->ring.tail = cur_read_ptr;
738 if (dev_priv->flags & RADEON_IS_AGP) {
740 dev_priv->ring_rptr->offset
741 - dev->agp->base + dev_priv->gart_vm_start);
746 dev_priv->ring_rptr->offset - dev->sg->vaddr +
747 dev_priv->gart_vm_start);
754 (dev_priv->ring.fetch_size_l2ow << 18) |
755 (dev_priv->ring.rptr_update_l2qw << 8) |
756 dev_priv->ring.size_l2qw);
759 (dev_priv->ring.fetch_size_l2ow << 18) |
760 (dev_priv->ring.rptr_update_l2qw << 8) |
761 dev_priv->ring.size_l2qw);
777 radeon_enable_bm(dev_priv);
779 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
782 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
785 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
789 if (dev_priv->sarea_priv) {
790 dev_priv->sarea_priv->last_frame = 0;
791 dev_priv->sarea_priv->last_dispatch = 0;
792 dev_priv->sarea_priv->last_clear = 0;
795 radeon_do_wait_for_idle(dev_priv);
806 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
811 dev_priv->writeback_works = 0;
816 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
820 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
823 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
829 if (tmp < dev_priv->usec_timeout) {
830 dev_priv->writeback_works = 1;
833 dev_priv->writeback_works = 0;
837 dev_priv->writeback_works = 0;
841 if (!dev_priv->writeback_works) {
850 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
856 dev_priv->gart_vm_start,
857 (long)dev_priv->gart_info.bus_addr,
858 dev_priv->gart_size);
860 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
861 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
862 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
871 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
877 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
878 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
881 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
885 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
887 dev_priv->gart_size = 32*1024*1024;
888 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
889 0xffff0000) | (dev_priv->gart_vm_start >> 16));
891 radeon_write_agp_location(dev_priv, temp);
893 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
898 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
908 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
921 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
928 dev_priv->gart_vm_start,
929 (long)dev_priv->gart_info.bus_addr,
930 dev_priv->gart_size);
953 dev_priv->gart_info.bus_addr);
955 dev_priv->gart_vm_start);
957 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
962 dev_priv->gart_vm_start);
964 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
967 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
970 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
974 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
978 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
982 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
986 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
990 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
996 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
998 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1002 dev_priv->gart_vm_start,
1003 (long)dev_priv->gart_info.bus_addr,
1004 dev_priv->gart_size);
1006 dev_priv->gart_vm_start);
1008 dev_priv->gart_info.bus_addr);
1010 dev_priv->gart_vm_start);
1012 dev_priv->gart_vm_start +
1013 dev_priv->gart_size - 1);
1015 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1026 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1030 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1031 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1032 (dev_priv->flags & RADEON_IS_IGPGART)) {
1033 radeon_set_igpgart(dev_priv, on);
1037 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1038 rs600_set_igpgart(dev_priv, on);
1042 if (dev_priv->flags & RADEON_IS_PCIE) {
1043 radeon_set_pciegart(dev_priv, on);
1055 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1059 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1060 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1061 + dev_priv->gart_size - 1);
1065 radeon_write_agp_location(dev_priv, 0xffffffc0);
1073 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1075 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1080 if (!dev_priv->virt_surfaces[i].file_priv ||
1081 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1086 vp = &dev_priv->virt_surfaces[i];
1089 struct radeon_surface *sp = &dev_priv->surfaces[i];
1116 drm_radeon_private_t *dev_priv = dev->dev_private;
1121 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1127 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1129 dev_priv->flags &= ~RADEON_IS_AGP;
1130 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1133 dev_priv->flags |= RADEON_IS_AGP;
1136 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1142 dev_priv->usec_timeout = init->usec_timeout;
1143 if (dev_priv->usec_timeout < 1 ||
1144 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1152 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1156 dev_priv->microcode_version = UCODE_R200;
1159 dev_priv->microcode_version = UCODE_R300;
1162 dev_priv->microcode_version = UCODE_R100;
1165 dev_priv->do_boxes = 0;
1166 dev_priv->cp_mode = init->cp_mode;
1181 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1185 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1188 dev_priv->front_offset = init->front_offset;
1189 dev_priv->front_pitch = init->front_pitch;
1190 dev_priv->back_offset = init->back_offset;
1191 dev_priv->back_pitch = init->back_pitch;
1195 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1199 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1202 dev_priv->depth_offset = init->depth_offset;
1203 dev_priv->depth_pitch = init->depth_pitch;
1210 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1211 (dev_priv->color_fmt << 10) |
1212 (dev_priv->microcode_version ==
1215 dev_priv->depth_clear.rb3d_zstencilcntl =
1216 (dev_priv->depth_fmt |
1223 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1236 dev_priv->ring_offset = init->ring_offset;
1237 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1238 dev_priv->buffers_offset = init->buffers_offset;
1239 dev_priv->gart_textures_offset = init->gart_textures_offset;
1241 dev_priv->sarea = drm_getsarea(dev);
1242 if (!dev_priv->sarea) {
1248 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1249 if (!dev_priv->cp_ring) {
1254 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1255 if (!dev_priv->ring_rptr) {
1269 dev_priv->gart_textures =
1271 if (!dev_priv->gart_textures) {
1278 dev_priv->sarea_priv =
1279 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->virtual +
1283 if (dev_priv->flags & RADEON_IS_AGP) {
1284 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1285 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1287 if (!dev_priv->cp_ring->virtual ||
1288 !dev_priv->ring_rptr->virtual ||
1297 dev_priv->cp_ring->virtual =
1298 (void *)(unsigned long)dev_priv->cp_ring->offset;
1299 dev_priv->ring_rptr->virtual =
1300 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1304 DRM_DEBUG("dev_priv->cp_ring->virtual %p\n",
1305 dev_priv->cp_ring->virtual);
1306 DRM_DEBUG("dev_priv->ring_rptr->virtual %p\n",
1307 dev_priv->ring_rptr->virtual);
1312 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1313 dev_priv->fb_size =
1314 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1315 - dev_priv->fb_location;
1317 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1318 ((dev_priv->front_offset
1319 + dev_priv->fb_location) >> 10));
1321 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1322 ((dev_priv->back_offset
1323 + dev_priv->fb_location) >> 10));
1325 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1326 ((dev_priv->depth_offset
1327 + dev_priv->fb_location) >> 10));
1329 dev_priv->gart_size = init->gart_size;
1332 if (dev_priv->new_memmap) {
1342 if (dev_priv->flags & RADEON_IS_AGP) {
1345 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1346 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1355 base = dev_priv->fb_location + dev_priv->fb_size;
1356 if (base < dev_priv->fb_location ||
1357 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1358 base = dev_priv->fb_location
1359 - dev_priv->gart_size;
1361 dev_priv->gart_vm_start = base & 0xffc00000u;
1362 if (dev_priv->gart_vm_start != base)
1364 base, dev_priv->gart_vm_start);
1367 dev_priv->gart_vm_start = dev_priv->fb_location +
1372 if (dev_priv->flags & RADEON_IS_AGP)
1373 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1375 + dev_priv->gart_vm_start);
1378 dev_priv->gart_buffers_offset = dev->agp_buffer_map->offset -
1379 dev->sg->vaddr + dev_priv->gart_vm_start;
1381 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1382 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1383 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1384 dev_priv->gart_buffers_offset);
1386 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual;
1387 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual
1389 dev_priv->ring.size = init->ring_size;
1390 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1392 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1393 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1395 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1396 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1397 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1399 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1402 if (dev_priv->flags & RADEON_IS_AGP) {
1404 radeon_set_pcigart(dev_priv, 0);
1411 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1413 if (dev_priv->pcigart_offset_set) {
1414 dev_priv->gart_info.bus_addr =
1415 dev_priv->pcigart_offset + dev_priv->fb_location;
1416 dev_priv->gart_info.mapping.offset =
1417 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1418 dev_priv->gart_info.mapping.size =
1419 dev_priv->gart_info.table_size;
1421 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1422 dev_priv->gart_info.addr =
1423 dev_priv->gart_info.mapping.virtual;
1425 if (dev_priv->flags & RADEON_IS_PCIE)
1426 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1428 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1429 dev_priv->gart_info.gart_table_location =
1433 dev_priv->gart_info.addr,
1434 dev_priv->pcigart_offset);
1436 if (dev_priv->flags & RADEON_IS_IGPGART)
1437 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1439 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1440 dev_priv->gart_info.gart_table_location =
1442 dev_priv->gart_info.addr = NULL;
1443 dev_priv->gart_info.bus_addr = 0;
1444 if (dev_priv->flags & RADEON_IS_PCIE) {
1454 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1457 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1466 ret = radeon_setup_pcigart_surface(dev_priv);
1469 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1470 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1472 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1478 radeon_set_pcigart(dev_priv, 1);
1481 radeon_cp_load_microcode(dev_priv);
1482 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1484 dev_priv->last_buf = 0;
1487 radeon_test_writeback(dev_priv);
1494 drm_radeon_private_t *dev_priv = dev->dev_private;
1505 if (dev_priv->flags & RADEON_IS_AGP) {
1506 if (dev_priv->cp_ring != NULL) {
1507 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1508 dev_priv->cp_ring = NULL;
1510 if (dev_priv->ring_rptr != NULL) {
1511 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1512 dev_priv->ring_rptr = NULL;
1522 if (dev_priv->gart_info.bus_addr) {
1524 radeon_set_pcigart(dev_priv, 0);
1525 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1526 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1528 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1533 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1535 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1536 dev_priv->gart_info.addr = 0;
1540 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1554 drm_radeon_private_t *dev_priv = dev->dev_private;
1556 if (!dev_priv) {
1564 if (dev_priv->flags & RADEON_IS_AGP) {
1566 radeon_set_pcigart(dev_priv, 0);
1571 radeon_set_pcigart(dev_priv, 1);
1574 radeon_cp_load_microcode(dev_priv);
1575 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1587 drm_radeon_private_t *dev_priv = dev->dev_private;
1603 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1614 drm_radeon_private_t *dev_priv = dev->dev_private;
1619 if (dev_priv->cp_running) {
1623 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1625 dev_priv->cp_mode);
1629 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1630 r600_do_cp_start(dev_priv);
1632 radeon_do_cp_start(dev_priv);
1642 drm_radeon_private_t *dev_priv = dev->dev_private;
1649 if (!dev_priv->cp_running)
1656 radeon_do_cp_flush(dev_priv);
1663 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1664 ret = r600_do_cp_idle(dev_priv);
1666 ret = radeon_do_cp_idle(dev_priv);
1675 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1676 r600_do_cp_stop(dev_priv);
1678 radeon_do_cp_stop(dev_priv);
1681 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1691 drm_radeon_private_t *dev_priv = dev->dev_private;
1694 if (dev_priv) {
1695 if (dev_priv->cp_running) {
1697 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1698 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1704 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1710 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1711 r600_do_cp_stop(dev_priv);
1714 radeon_do_cp_stop(dev_priv);
1719 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1721 if (dev_priv->mmio) /* remove this after permanent addmaps */
1724 if (dev_priv->mmio) { /* remove all surfaces */
1736 radeon_mem_takedown(&(dev_priv->gart_heap));
1737 radeon_mem_takedown(&(dev_priv->fb_heap));
1740 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1751 drm_radeon_private_t *dev_priv = dev->dev_private;
1756 if (!dev_priv) {
1761 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1762 r600_do_cp_reset(dev_priv);
1764 radeon_do_cp_reset(dev_priv);
1767 dev_priv->cp_running = 0;
1774 drm_radeon_private_t *dev_priv = dev->dev_private;
1779 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1780 return r600_do_cp_idle(dev_priv);
1782 return radeon_do_cp_idle(dev_priv);
1789 drm_radeon_private_t *dev_priv = dev->dev_private;
1792 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1800 drm_radeon_private_t *dev_priv = dev->dev_private;
1805 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1846 drm_radeon_private_t *dev_priv = dev->dev_private;
1852 if (++dev_priv->last_buf >= dma->buf_count)
1853 dev_priv->last_buf = 0;
1855 start = dev_priv->last_buf;
1857 for (t = 0; t < dev_priv->usec_timeout; t++) {
1858 u32 done_age = GET_SCRATCH(dev_priv, 1);
1866 dev_priv->stats.requested_bufs++;
1876 dev_priv->stats.freelist_loops++;
1886 drm_radeon_private_t *dev_priv = dev->dev_private;
1889 dev_priv->last_buf = 0;
1901 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1903 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1905 u32 last_head = GET_RING_HEAD(dev_priv);
1907 for (i = 0; i < dev_priv->usec_timeout; i++) {
1908 u32 head = GET_RING_HEAD(dev_priv);
1916 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1927 radeon_status(dev_priv);
1994 drm_radeon_private_t *dev_priv;
1997 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1998 if (dev_priv == NULL)
2001 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2002 dev->dev_private = (void *)dev_priv;
2003 dev_priv->flags = flags;
2018 dev_priv->flags |= RADEON_HAS_HIERZ;
2026 dev_priv->flags |= RADEON_IS_AGP;
2028 dev_priv->flags |= RADEON_IS_PCIE;
2030 dev_priv->flags |= RADEON_IS_PCI;
2032 mtx_init(&dev_priv->cs.cs_mutex, "cs_mtx", NULL, MTX_DEF);
2036 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2047 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" :
2048 (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2064 drm_radeon_private_t *dev_priv = dev->dev_private;
2066 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2068 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2069 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2080 drm_radeon_private_t *dev_priv = dev->dev_private;
2084 drm_rmmap(dev, dev_priv->mmio);
2086 mtx_destroy(&dev_priv->cs.cs_mutex);
2088 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2094 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2102 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1);
2106 ring = dev_priv->ring.start;
2109 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2111 dev_priv->ring.tail += i;
2113 dev_priv->ring.space -= num_p2 * sizeof(u32);
2116 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2119 GET_RING_HEAD( dev_priv );
2121 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2122 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2126 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);