dev/drm/radeon_cp.c

610 	dev_priv->ring.tail = cur_read_ptr;
681 	/* Reset the CP ring */
731 	/* Initialize the ring buffer's read and write pointers */
735 	dev_priv->ring.tail = cur_read_ptr;
750 	/* Set ring buffer size */
754 		     (dev_priv->ring.fetch_size_l2ow << 18) |
755 		     (dev_priv->ring.rptr_update_l2qw << 8) |
756 		     dev_priv->ring.size_l2qw);
759 		     (dev_priv->ring.fetch_size_l2ow << 18) |
760 		     (dev_priv->ring.rptr_update_l2qw << 8) |
761 		     dev_priv->ring.size_l2qw);
769 	 * We simply put this behind the ring read pointer, this works
1168 	/* We don't support anything other than bus-mastering ring mode,
1169 	 * but the ring can be in either AGP or PCI space for the ring
1250 		DRM_ERROR("could not find cp ring region!\n");
1256 		DRM_ERROR("could not find ring read pointer!\n");
1386 	dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual;
1387 	dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual
1389 	dev_priv->ring.size = init->ring_size;
1390 	dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1392 	dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1393 	dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1395 	dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1396 	dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1397 	dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1399 	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1747 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1903 	drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1910 		ring->space = (head - ring->tail) * sizeof(u32);
1911 		if (ring->space <= 0)
1912 			ring->space += ring->size;
1913 		if (ring->space > n)
2097 	u32 *ring;
2100 	/* check if the ring is padded out to 16-dword alignment */
2102 	tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1);
2106 		ring = dev_priv->ring.start;
2109 			ring[dev_priv->ring.tail + i] = CP_PACKET2();
2111 		dev_priv->ring.tail += i;
2113 		dev_priv->ring.space -= num_p2 * sizeof(u32);
2116 	dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2122 		RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2126 		RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);