Lines Matching refs:dev_priv
71 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
75 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
77 for (i = 0; i < dev_priv->usec_timeout; i++) {
79 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
96 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
100 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
102 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
103 ret = r600_do_wait_for_fifo(dev_priv, 8);
105 ret = r600_do_wait_for_fifo(dev_priv, 16);
108 for (i = 0; i < dev_priv->usec_timeout; i++) {
149 drm_radeon_private_t *dev_priv = dev->dev_private;
150 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
204 drm_radeon_private_t *dev_priv = dev->dev_private;
206 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
207 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
219 drm_radeon_private_t *dev_priv = dev->dev_private;
225 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
226 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
275 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
276 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
277 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
283 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
289 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
330 r600_do_cp_stop(dev_priv);
361 drm_radeon_private_t *dev_priv = dev->dev_private;
367 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
368 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
404 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
405 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
406 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
412 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
418 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
439 r600_do_cp_stop(dev_priv);
466 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
471 dev_priv->writeback_works = 0;
476 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
480 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
483 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
489 if (tmp < dev_priv->usec_timeout) {
490 dev_priv->writeback_works = 1;
493 dev_priv->writeback_works = 0;
497 dev_priv->writeback_works = 0;
501 if (!dev_priv->writeback_works) {
511 drm_radeon_private_t *dev_priv = dev->dev_private;
536 r600_do_cp_reset(dev_priv);
539 dev_priv->cp_running = 0;
668 drm_radeon_private_t *dev_priv)
692 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
694 dev_priv->r600_max_pipes = 4;
695 dev_priv->r600_max_tile_pipes = 8;
696 dev_priv->r600_max_simds = 4;
697 dev_priv->r600_max_backends = 4;
698 dev_priv->r600_max_gprs = 256;
699 dev_priv->r600_max_threads = 192;
700 dev_priv->r600_max_stack_entries = 256;
701 dev_priv->r600_max_hw_contexts = 8;
702 dev_priv->r600_max_gs_threads = 16;
703 dev_priv->r600_sx_max_export_size = 128;
704 dev_priv->r600_sx_max_export_pos_size = 16;
705 dev_priv->r600_sx_max_export_smx_size = 128;
706 dev_priv->r600_sq_num_cf_insts = 2;
710 dev_priv->r600_max_pipes = 2;
711 dev_priv->r600_max_tile_pipes = 2;
712 dev_priv->r600_max_simds = 3;
713 dev_priv->r600_max_backends = 1;
714 dev_priv->r600_max_gprs = 128;
715 dev_priv->r600_max_threads = 192;
716 dev_priv->r600_max_stack_entries = 128;
717 dev_priv->r600_max_hw_contexts = 8;
718 dev_priv->r600_max_gs_threads = 4;
719 dev_priv->r600_sx_max_export_size = 128;
720 dev_priv->r600_sx_max_export_pos_size = 16;
721 dev_priv->r600_sx_max_export_smx_size = 128;
722 dev_priv->r600_sq_num_cf_insts = 2;
728 dev_priv->r600_max_pipes = 1;
729 dev_priv->r600_max_tile_pipes = 1;
730 dev_priv->r600_max_simds = 2;
731 dev_priv->r600_max_backends = 1;
732 dev_priv->r600_max_gprs = 128;
733 dev_priv->r600_max_threads = 192;
734 dev_priv->r600_max_stack_entries = 128;
735 dev_priv->r600_max_hw_contexts = 4;
736 dev_priv->r600_max_gs_threads = 4;
737 dev_priv->r600_sx_max_export_size = 128;
738 dev_priv->r600_sx_max_export_pos_size = 16;
739 dev_priv->r600_sx_max_export_smx_size = 128;
740 dev_priv->r600_sq_num_cf_insts = 1;
743 dev_priv->r600_max_pipes = 4;
744 dev_priv->r600_max_tile_pipes = 4;
745 dev_priv->r600_max_simds = 4;
746 dev_priv->r600_max_backends = 4;
747 dev_priv->r600_max_gprs = 192;
748 dev_priv->r600_max_threads = 192;
749 dev_priv->r600_max_stack_entries = 256;
750 dev_priv->r600_max_hw_contexts = 8;
751 dev_priv->r600_max_gs_threads = 16;
752 dev_priv->r600_sx_max_export_size = 128;
753 dev_priv->r600_sx_max_export_pos_size = 16;
754 dev_priv->r600_sx_max_export_smx_size = 128;
755 dev_priv->r600_sq_num_cf_insts = 2;
777 switch (dev_priv->r600_max_tile_pipes) {
810 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
811 dev_priv->r600_max_backends,
812 (0xff << dev_priv->r600_max_backends) & 0xff);
816 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
818 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
821 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
848 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
853 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
857 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
858 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
859 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
860 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
861 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
862 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
878 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
879 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
880 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
881 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
886 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
887 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
908 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
922 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
925 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
942 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
943 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
957 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
980 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
981 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
982 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
983 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1018 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1037 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1069 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1214 drm_radeon_private_t *dev_priv)
1235 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1237 dev_priv->r600_max_pipes = 4;
1238 dev_priv->r600_max_tile_pipes = 8;
1239 dev_priv->r600_max_simds = 10;
1240 dev_priv->r600_max_backends = 4;
1241 dev_priv->r600_max_gprs = 256;
1242 dev_priv->r600_max_threads = 248;
1243 dev_priv->r600_max_stack_entries = 512;
1244 dev_priv->r600_max_hw_contexts = 8;
1245 dev_priv->r600_max_gs_threads = 16 * 2;
1246 dev_priv->r600_sx_max_export_size = 128;
1247 dev_priv->r600_sx_max_export_pos_size = 16;
1248 dev_priv->r600_sx_max_export_smx_size = 112;
1249 dev_priv->r600_sq_num_cf_insts = 2;
1251 dev_priv->r700_sx_num_of_sets = 7;
1252 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1253 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1254 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1257 dev_priv->r600_max_pipes = 4;
1258 dev_priv->r600_max_tile_pipes = 4;
1259 dev_priv->r600_max_simds = 8;
1260 dev_priv->r600_max_backends = 4;
1261 dev_priv->r600_max_gprs = 256;
1262 dev_priv->r600_max_threads = 248;
1263 dev_priv->r600_max_stack_entries = 512;
1264 dev_priv->r600_max_hw_contexts = 8;
1265 dev_priv->r600_max_gs_threads = 16 * 2;
1266 dev_priv->r600_sx_max_export_size = 256;
1267 dev_priv->r600_sx_max_export_pos_size = 32;
1268 dev_priv->r600_sx_max_export_smx_size = 224;
1269 dev_priv->r600_sq_num_cf_insts = 2;
1271 dev_priv->r700_sx_num_of_sets = 7;
1272 dev_priv->r700_sc_prim_fifo_size = 0x100;
1273 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1274 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1276 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1277 dev_priv->r600_sx_max_export_pos_size -= 16;
1278 dev_priv->r600_sx_max_export_smx_size += 16;
1282 dev_priv->r600_max_pipes = 2;
1283 dev_priv->r600_max_tile_pipes = 4;
1284 dev_priv->r600_max_simds = 8;
1285 dev_priv->r600_max_backends = 2;
1286 dev_priv->r600_max_gprs = 128;
1287 dev_priv->r600_max_threads = 248;
1288 dev_priv->r600_max_stack_entries = 256;
1289 dev_priv->r600_max_hw_contexts = 8;
1290 dev_priv->r600_max_gs_threads = 16 * 2;
1291 dev_priv->r600_sx_max_export_size = 256;
1292 dev_priv->r600_sx_max_export_pos_size = 32;
1293 dev_priv->r600_sx_max_export_smx_size = 224;
1294 dev_priv->r600_sq_num_cf_insts = 2;
1296 dev_priv->r700_sx_num_of_sets = 7;
1297 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1298 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1299 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1301 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1302 dev_priv->r600_sx_max_export_pos_size -= 16;
1303 dev_priv->r600_sx_max_export_smx_size += 16;
1307 dev_priv->r600_max_pipes = 2;
1308 dev_priv->r600_max_tile_pipes = 2;
1309 dev_priv->r600_max_simds = 2;
1310 dev_priv->r600_max_backends = 1;
1311 dev_priv->r600_max_gprs = 256;
1312 dev_priv->r600_max_threads = 192;
1313 dev_priv->r600_max_stack_entries = 256;
1314 dev_priv->r600_max_hw_contexts = 4;
1315 dev_priv->r600_max_gs_threads = 8 * 2;
1316 dev_priv->r600_sx_max_export_size = 128;
1317 dev_priv->r600_sx_max_export_pos_size = 16;
1318 dev_priv->r600_sx_max_export_smx_size = 112;
1319 dev_priv->r600_sq_num_cf_insts = 1;
1321 dev_priv->r700_sx_num_of_sets = 7;
1322 dev_priv->r700_sc_prim_fifo_size = 0x40;
1323 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1324 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1346 switch (dev_priv->r600_max_tile_pipes) {
1363 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1382 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1383 dev_priv->r600_max_backends,
1384 (0xff << dev_priv->r600_max_backends) & 0xff);
1388 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1390 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1393 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1431 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1439 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1447 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1448 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1449 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1451 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1452 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1453 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1465 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1468 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1496 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1502 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1503 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1504 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1506 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1507 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1509 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1510 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1511 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1512 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1513 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1515 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1518 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1519 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1521 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1522 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1524 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1525 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1526 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1527 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1541 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1548 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1561 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1608 drm_radeon_private_t *dev_priv,
1614 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1615 r700_gfx_init(dev, dev_priv);
1617 r600_gfx_init(dev, dev_priv);
1630 (dev_priv->ring.rptr_update_l2qw << 8) |
1631 dev_priv->ring.size_l2qw);
1635 (dev_priv->ring.rptr_update_l2qw << 8) |
1636 dev_priv->ring.size_l2qw);
1649 (dev_priv->ring.rptr_update_l2qw << 8) |
1650 dev_priv->ring.size_l2qw);
1655 (dev_priv->ring.rptr_update_l2qw << 8) |
1656 dev_priv->ring.size_l2qw);
1662 SET_RING_HEAD(dev_priv, 0);
1663 dev_priv->ring.tail = 0;
1666 if (dev_priv->flags & RADEON_IS_AGP) {
1667 rptr_addr = dev_priv->ring_rptr->offset
1669 dev_priv->gart_vm_start;
1673 rptr_addr = dev_priv->ring_rptr->offset - dev->sg->vaddr +
1674 dev_priv->gart_vm_start;
1684 (dev_priv->ring.rptr_update_l2qw << 8) |
1685 dev_priv->ring.size_l2qw);
1688 (dev_priv->ring.rptr_update_l2qw << 8) |
1689 dev_priv->ring.size_l2qw);
1693 if (dev_priv->flags & RADEON_IS_AGP) {
1695 radeon_write_agp_base(dev_priv, dev->agp->base);
1698 radeon_write_agp_location(dev_priv,
1699 (((dev_priv->gart_vm_start - 1 +
1700 dev_priv->gart_size) & 0xffff0000) |
1701 (dev_priv->gart_vm_start >> 16)));
1703 ring_start = (dev_priv->cp_ring->offset
1705 + dev_priv->gart_vm_start);
1708 ring_start = dev_priv->cp_ring->offset - dev->sg->vaddr +
1709 dev_priv->gart_vm_start;
1739 radeon_enable_bm(dev_priv);
1741 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1744 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1747 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1751 if (dev_priv->sarea_priv) {
1752 dev_priv->sarea_priv->last_frame = 0;
1753 dev_priv->sarea_priv->last_dispatch = 0;
1754 dev_priv->sarea_priv->last_clear = 0;
1757 r600_do_wait_for_idle(dev_priv);
1763 drm_radeon_private_t *dev_priv = dev->dev_private;
1774 if (dev_priv->flags & RADEON_IS_AGP) {
1775 if (dev_priv->cp_ring != NULL) {
1776 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1777 dev_priv->cp_ring = NULL;
1779 if (dev_priv->ring_rptr != NULL) {
1780 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1781 dev_priv->ring_rptr = NULL;
1791 if (dev_priv->gart_info.bus_addr)
1792 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1794 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1795 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1796 dev_priv->gart_info.addr = 0;
1800 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1808 drm_radeon_private_t *dev_priv = dev->dev_private;
1813 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1819 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1821 dev_priv->flags &= ~RADEON_IS_AGP;
1826 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1829 dev_priv->flags |= RADEON_IS_AGP;
1832 dev_priv->usec_timeout = init->usec_timeout;
1833 if (dev_priv->usec_timeout < 1 ||
1834 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1842 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1844 dev_priv->do_boxes = 0;
1845 dev_priv->cp_mode = init->cp_mode;
1860 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1864 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1867 dev_priv->front_offset = init->front_offset;
1868 dev_priv->front_pitch = init->front_pitch;
1869 dev_priv->back_offset = init->back_offset;
1870 dev_priv->back_pitch = init->back_pitch;
1872 dev_priv->ring_offset = init->ring_offset;
1873 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1874 dev_priv->buffers_offset = init->buffers_offset;
1875 dev_priv->gart_textures_offset = init->gart_textures_offset;
1877 dev_priv->sarea = drm_getsarea(dev);
1878 if (!dev_priv->sarea) {
1884 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1885 if (!dev_priv->cp_ring) {
1890 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1891 if (!dev_priv->ring_rptr) {
1905 dev_priv->gart_textures =
1907 if (!dev_priv->gart_textures) {
1914 dev_priv->sarea_priv =
1915 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->virtual +
1920 if (dev_priv->flags & RADEON_IS_AGP) {
1921 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1922 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1924 if (!dev_priv->cp_ring->virtual ||
1925 !dev_priv->ring_rptr->virtual ||
1934 dev_priv->cp_ring->virtual =
1935 (void *)dev_priv->cp_ring->offset;
1936 dev_priv->ring_rptr->virtual =
1937 (void *)dev_priv->ring_rptr->offset;
1941 DRM_DEBUG("dev_priv->cp_ring->virtual %p\n",
1942 dev_priv->cp_ring->virtual);
1943 DRM_DEBUG("dev_priv->ring_rptr->virtual %p\n",
1944 dev_priv->ring_rptr->virtual);
1949 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1950 dev_priv->fb_size =
1951 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1952 - dev_priv->fb_location;
1954 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1955 ((dev_priv->front_offset
1956 + dev_priv->fb_location) >> 10));
1958 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1959 ((dev_priv->back_offset
1960 + dev_priv->fb_location) >> 10));
1962 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1963 ((dev_priv->depth_offset
1964 + dev_priv->fb_location) >> 10));
1966 dev_priv->gart_size = init->gart_size;
1969 if (dev_priv->new_memmap) {
1980 if (dev_priv->flags & RADEON_IS_AGP) {
1983 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1984 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1993 base = dev_priv->fb_location + dev_priv->fb_size;
1994 if (base < dev_priv->fb_location ||
1995 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1996 base = dev_priv->fb_location
1997 - dev_priv->gart_size;
1999 dev_priv->gart_vm_start = base & 0xffc00000u;
2000 if (dev_priv->gart_vm_start != base)
2002 base, dev_priv->gart_vm_start);
2007 if (dev_priv->flags & RADEON_IS_AGP)
2008 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2010 + dev_priv->gart_vm_start);
2013 dev_priv->gart_buffers_offset = dev->agp_buffer_map->offset -
2014 dev->sg->vaddr + dev_priv->gart_vm_start;
2017 (unsigned int) dev_priv->fb_location,
2018 (unsigned int) dev_priv->fb_size);
2019 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2020 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2021 (unsigned int) dev_priv->gart_vm_start);
2022 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2023 dev_priv->gart_buffers_offset);
2025 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual;
2026 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual
2028 dev_priv->ring.size = init->ring_size;
2029 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2031 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2032 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2034 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2035 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2037 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2039 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2042 if (dev_priv->flags & RADEON_IS_AGP) {
2047 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2049 if (!dev_priv->pcigart_offset_set) {
2055 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2057 dev_priv->gart_info.bus_addr =
2058 dev_priv->pcigart_offset + dev_priv->fb_location;
2059 dev_priv->gart_info.mapping.offset =
2060 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2061 dev_priv->gart_info.mapping.size =
2062 dev_priv->gart_info.table_size;
2064 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2065 if (!dev_priv->gart_info.mapping.virtual) {
2071 dev_priv->gart_info.addr =
2072 dev_priv->gart_info.mapping.virtual;
2075 dev_priv->gart_info.addr,
2076 dev_priv->pcigart_offset);
2084 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2090 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2091 r700_cp_load_microcode(dev_priv);
2093 r600_cp_load_microcode(dev_priv);
2095 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2097 dev_priv->last_buf = 0;
2100 r600_test_writeback(dev_priv);
2109 drm_radeon_private_t *dev_priv = dev->dev_private;
2112 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2114 r700_cp_load_microcode(dev_priv);
2117 r600_cp_load_microcode(dev_priv);
2119 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2127 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2143 return r600_do_wait_for_idle(dev_priv);
2148 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2157 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2161 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2172 dev_priv->cp_running = 1;
2176 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2183 SET_RING_HEAD(dev_priv, cur_read_ptr);
2184 dev_priv->ring.tail = cur_read_ptr;
2187 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2197 dev_priv->cp_running = 0;
2203 drm_radeon_private_t *dev_priv = dev->dev_private;
2207 unsigned long offset = (dev_priv->gart_buffers_offset
2239 drm_radeon_private_t *dev_priv = dev->dev_private;
2240 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2248 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2253 if (dev_priv->sarea_priv->pfCurrentPage == 0) {
2254 src_pitch = dev_priv->back_pitch;
2255 dst_pitch = dev_priv->front_pitch;
2256 src = dev_priv->back_offset + dev_priv->fb_location;
2257 dst = dev_priv->front_offset + dev_priv->fb_location;
2259 src_pitch = dev_priv->front_pitch;
2260 dst_pitch = dev_priv->back_pitch;
2261 src = dev_priv->front_offset + dev_priv->fb_location;
2262 dst = dev_priv->back_offset + dev_priv->fb_location;
2288 dev_priv->sarea_priv->last_frame++;
2291 R600_FRAME_AGE(dev_priv->sarea_priv->last_frame);
2300 drm_radeon_private_t *dev_priv = dev->dev_private;
2307 if (!radeon_check_offset(dev_priv, tex->offset)) {
2313 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2354 src_offset = dev_priv->gart_buffers_offset + buf->offset;