dev/drm/r300_cmdbuf.c

58 static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
86 			if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
155 	dev_priv->track_flush |= RADEON_FLUSH_EMITED;
165 	drm_radeon_private_t *dev_priv = dev->dev_private;
212 	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530)
261 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
297 							  dev_priv,
324 			if (!radeon_check_offset(dev_priv, (u32) values[i])) {
355 static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
381 		return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
402 static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
429 	dev_priv->track_flush |= RADEON_FLUSH_EMITED;
452 static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
474 	dev_priv->track_flush |= RADEON_FLUSH_EMITED;
482 static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
509 		if (!radeon_check_offset(dev_priv, payload[i])) {
520 		if (!radeon_check_offset(dev_priv, payload[i])) {
550 static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
565 			ret = !radeon_check_offset(dev_priv, offset);
575 			ret = !radeon_check_offset(dev_priv, offset);
595 static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv,
648 		if (!radeon_check_offset(dev_priv, cmd[2])) {
670 static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
705 		return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
708 		return r300_emit_bitblt_multi(dev_priv, cmdbuf);
717 		dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
723 		dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
725 		return r300_emit_draw_indx_2(dev_priv, cmdbuf);
750 static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
765 			ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
776 			ret = r300_emit_clear(dev_priv, cmdbuf);
785 			ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
819 static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
827 	if (!(dev_priv->track_flush & RADEON_PURGE_EMITED)) {
867 	dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
877 	drm_radeon_private_t *dev_priv = dev->dev_private;
880 	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
885 static void r300_cmd_wait(drm_radeon_private_t * dev_priv,
926 static int r300_scratch(drm_radeon_private_t *dev_priv,
942 	dev_priv->scratch_ages[header.scratch.reg] ++;
953 		if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
977 	OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
988 static __inline__ int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
1040 	drm_radeon_private_t *dev_priv = dev->dev_private;
1049 	r300_pacify(dev_priv);
1052 		ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
1068 			ret = r300_emit_packet0(dev_priv, cmdbuf, header);
1077 			ret = r300_emit_vpu(dev_priv, cmdbuf, header);
1086 			ret = r300_emit_packet3(dev_priv, cmdbuf, header);
1110 			r300_pacify(dev_priv);
1152 			r300_cmd_wait(dev_priv, header);
1157 			ret = r300_scratch(dev_priv, cmdbuf, header);
1165 			if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1171 			ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
1189 	r300_pacify(dev_priv);
1202 		RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);