dev/drm/r128_cce.c

89 	drm_r128_private_t *dev_priv = dev->dev_private;
96 static void r128_status(drm_r128_private_t * dev_priv)
117 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
125 	for (i = 0; i < dev_priv->usec_timeout; i++) {
138 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
142 	for (i = 0; i < dev_priv->usec_timeout; i++) {
155 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
159 	ret = r128_do_wait_for_fifo(dev_priv, 64);
163 	for (i = 0; i < dev_priv->usec_timeout; i++) {
165 			r128_do_pixcache_flush(dev_priv);
182 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
188 	r128_do_wait_for_idle(dev_priv);
202 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
212 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
216 	for (i = 0; i < dev_priv->usec_timeout; i++) {
217 		if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
220 			     dev_priv->cce_fifo_size) &&
223 				return r128_do_pixcache_flush(dev_priv);
231 	r128_status(dev_priv);
238 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
240 	r128_do_wait_for_idle(dev_priv);
243 		   dev_priv->cce_mode | dev_priv->ring.size_l2qw
248 	dev_priv->cce_running = 1;
255 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
259 	dev_priv->ring.tail = 0;
266 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
272 	dev_priv->cce_running = 0;
279 	drm_r128_private_t *dev_priv = dev->dev_private;
282 	r128_do_pixcache_flush(dev_priv);
303 	r128_do_cce_reset(dev_priv);
306 	dev_priv->cce_running = 0;
315 				      drm_r128_private_t * dev_priv)
326 	if (!dev_priv->is_pci)
327 		ring_start = dev_priv->cce_ring->offset - dev->agp->base;
330 		ring_start = dev_priv->cce_ring->offset - dev->sg->vaddr;
354 	drm_r128_private_t *dev_priv;
358 	dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
359 	if (dev_priv == NULL)
362 	memset(dev_priv, 0, sizeof(drm_r128_private_t));
364 	dev_priv->is_pci = init->is_pci;
366 	if (dev_priv->is_pci && !dev->sg) {
368 		dev->dev_private = (void *)dev_priv;
373 	dev_priv->usec_timeout = init->usec_timeout;
374 	if (dev_priv->usec_timeout < 1 ||
375 	    dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
377 		dev->dev_private = (void *)dev_priv;
382 	dev_priv->cce_mode = init->cce_mode;
386 	atomic_set(&dev_priv->idle_count, 0);
397 		dev->dev_private = (void *)dev_priv;
404 		dev_priv->cce_fifo_size = 0;
408 		dev_priv->cce_fifo_size = 192;
412 		dev_priv->cce_fifo_size = 128;
419 		dev_priv->cce_fifo_size = 64;
425 		dev_priv->color_fmt = R128_DATATYPE_RGB565;
429 		dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
432 	dev_priv->front_offset = init->front_offset;
433 	dev_priv->front_pitch = init->front_pitch;
434 	dev_priv->back_offset = init->back_offset;
435 	dev_priv->back_pitch = init->back_pitch;
439 		dev_priv->depth_fmt = R128_DATATYPE_RGB565;
444 		dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
447 	dev_priv->depth_offset = init->depth_offset;
448 	dev_priv->depth_pitch = init->depth_pitch;
449 	dev_priv->span_offset = init->span_offset;
451 	dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
452 					  (dev_priv->front_offset >> 5));
453 	dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
454 					 (dev_priv->back_offset >> 5));
455 	dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
456 					  (dev_priv->depth_offset >> 5) |
458 	dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
459 					 (dev_priv->span_offset >> 5));
461 	dev_priv->sarea = drm_getsarea(dev);
462 	if (!dev_priv->sarea) {
464 		dev->dev_private = (void *)dev_priv;
469 	dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
470 	if (!dev_priv->mmio) {
472 		dev->dev_private = (void *)dev_priv;
476 	dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
477 	if (!dev_priv->cce_ring) {
479 		dev->dev_private = (void *)dev_priv;
483 	dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
484 	if (!dev_priv->ring_rptr) {
486 		dev->dev_private = (void *)dev_priv;
494 		dev->dev_private = (void *)dev_priv;
499 	if (!dev_priv->is_pci) {
500 		dev_priv->agp_textures =
502 		if (!dev_priv->agp_textures) {
504 			dev->dev_private = (void *)dev_priv;
510 	dev_priv->sarea_priv =
511 	    (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->virtual +
515 	if (!dev_priv->is_pci) {
516 		drm_core_ioremap(dev_priv->cce_ring, dev);
517 		drm_core_ioremap(dev_priv->ring_rptr, dev);
519 		if (!dev_priv->cce_ring->virtual ||
520 		    !dev_priv->ring_rptr->virtual ||
523 			dev->dev_private = (void *)dev_priv;
530 		dev_priv->cce_ring->virtual =
531 		    (void *)dev_priv->cce_ring->offset;
532 		dev_priv->ring_rptr->virtual =
533 		    (void *)dev_priv->ring_rptr->offset;
539 	if (!dev_priv->is_pci)
540 		dev_priv->cce_buffers_offset = dev->agp->base;
543 		dev_priv->cce_buffers_offset = dev->sg->vaddr;
545 	dev_priv->ring.start = (u32 *) dev_priv->cce_ring->virtual;
546 	dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->virtual
548 	dev_priv->ring.size = init->ring_size;
549 	dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
551 	dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
553 	dev_priv->ring.high_mark = 128;
555 	dev_priv->sarea_priv->last_frame = 0;
556 	R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
558 	dev_priv->sarea_priv->last_dispatch = 0;
559 	R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
562 	if (dev_priv->is_pci) {
564 		dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
565 		dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
566 		dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
567 		dev_priv->gart_info.addr = NULL;
568 		dev_priv->gart_info.bus_addr = 0;
569 		dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
570 		if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
572 			dev->dev_private = (void *)dev_priv;
576 		R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
581 	r128_cce_init_ring_buffer(dev, dev_priv);
582 	r128_cce_load_microcode(dev_priv);
584 	dev->dev_private = (void *)dev_priv;
602 		drm_r128_private_t *dev_priv = dev->dev_private;
605 		if (!dev_priv->is_pci) {
606 			if (dev_priv->cce_ring != NULL)
607 				drm_core_ioremapfree(dev_priv->cce_ring, dev);
608 			if (dev_priv->ring_rptr != NULL)
609 				drm_core_ioremapfree(dev_priv->ring_rptr, dev);
617 			if (dev_priv->gart_info.bus_addr)
618 				if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
650 	drm_r128_private_t *dev_priv = dev->dev_private;
655 	if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
660 	r128_do_cce_start(dev_priv);
670 	drm_r128_private_t *dev_priv = dev->dev_private;
681 		r128_do_cce_flush(dev_priv);
688 		ret = r128_do_cce_idle(dev_priv);
697 	r128_do_cce_stop(dev_priv);
709 	drm_r128_private_t *dev_priv = dev->dev_private;
714 	if (!dev_priv) {
719 	r128_do_cce_reset(dev_priv);
722 	dev_priv->cce_running = 0;
729 	drm_r128_private_t *dev_priv = dev->dev_private;
734 	if (dev_priv->cce_running) {
735 		r128_do_cce_flush(dev_priv);
738 	return r128_do_cce_idle(dev_priv);
765 	drm_r128_private_t *dev_priv = dev->dev_private;
771 	dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
772 	if (dev_priv->head == NULL)
775 	memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
776 	dev_priv->head->age = R128_BUFFER_USED;
788 		entry->prev = dev_priv->head;
789 		entry->next = dev_priv->head->next;
791 			dev_priv->tail = entry;
797 		dev_priv->head->next = entry;
799 		if (dev_priv->head->next)
800 			dev_priv->head->next->prev = entry;
811 	drm_r128_private_t *dev_priv = dev->dev_private;
825 	for (t = 0; t < dev_priv->usec_timeout; t++) {
862 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
864 	drm_r128_ring_buffer_t *ring = &dev_priv->ring;
867 	for (i = 0; i < dev_priv->usec_timeout; i++) {
868 		r128_update_ring_snapshot(dev_priv);