Lines Matching defs:dev_priv
40 struct drm_i915_private *dev_priv = dev->dev_private;
50 struct drm_i915_private *dev_priv = dev->dev_private;
59 array = dev_priv->save_palette_a;
61 array = dev_priv->save_palette_b;
69 struct drm_i915_private *dev_priv = dev->dev_private;
78 array = dev_priv->save_palette_a;
80 array = dev_priv->save_palette_b;
88 struct drm_i915_private *dev_priv = dev->dev_private;
96 struct drm_i915_private *dev_priv = dev->dev_private;
105 struct drm_i915_private *dev_priv = dev->dev_private;
114 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct drm_i915_private *dev_priv = dev->dev_private;
127 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
130 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
131 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
146 dev_priv->saveCR[i] =
149 dev_priv->saveCR[0x11] &= ~0x80;
153 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
155 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
157 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
162 dev_priv->saveGR[i] =
165 dev_priv->saveGR[0x10] =
167 dev_priv->saveGR[0x11] =
169 dev_priv->saveGR[0x18] =
174 dev_priv->saveSR[i] =
180 struct drm_i915_private *dev_priv = dev->dev_private;
185 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
186 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
199 dev_priv->saveSR[i]);
203 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
205 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
210 dev_priv->saveGR[i]);
213 dev_priv->saveGR[0x10]);
215 dev_priv->saveGR[0x11]);
217 dev_priv->saveGR[0x18]);
222 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
224 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
228 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
233 struct drm_i915_private *dev_priv = dev->dev_private;
237 dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1);
239 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
244 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
247 dev_priv->saveHWS = I915_READ(HWS_PGA);
250 dev_priv->saveDSPARB = I915_READ(DSPARB);
253 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
254 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
255 dev_priv->saveFPA0 = I915_READ(FPA0);
256 dev_priv->saveFPA1 = I915_READ(FPA1);
257 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
259 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
260 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
261 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
262 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
263 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
264 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
265 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
266 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
268 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
269 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
270 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
271 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
272 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
274 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
275 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
278 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
281 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
282 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
283 dev_priv->saveFPB0 = I915_READ(FPB0);
284 dev_priv->saveFPB1 = I915_READ(FPB1);
285 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
287 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
288 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
289 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
290 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
291 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
292 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
293 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
294 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
296 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
297 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
298 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
299 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
300 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
302 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
303 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
306 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
309 dev_priv->saveADPA = I915_READ(ADPA);
312 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
313 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
314 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
316 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
318 dev_priv->saveLVDS = I915_READ(LVDS);
320 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
321 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
322 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
323 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
328 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
329 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
330 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
331 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
334 dev_priv->saveIIR = I915_READ(IIR);
335 dev_priv->saveIER = I915_READ(IER);
336 dev_priv->saveIMR = I915_READ(IMR);
339 dev_priv->saveVGA0 = I915_READ(VGA0);
340 dev_priv->saveVGA1 = I915_READ(VGA1);
341 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
342 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
345 dev_priv->saveD_STATE = I915_READ(D_STATE);
346 dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
349 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
352 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
356 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
357 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
360 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
369 struct drm_i915_private *dev_priv = dev->dev_private;
373 pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1);
375 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
380 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
383 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
386 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
390 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
391 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
395 I915_WRITE(FPA0, dev_priv->saveFPA0);
396 I915_WRITE(FPA1, dev_priv->saveFPA1);
398 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
401 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
405 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
406 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
407 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
408 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
409 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
410 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
411 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
414 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
415 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
416 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
417 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
418 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
420 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
421 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
424 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
428 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
432 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
433 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
437 I915_WRITE(FPB0, dev_priv->saveFPB0);
438 I915_WRITE(FPB1, dev_priv->saveFPB1);
440 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
443 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
447 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
448 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
449 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
450 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
451 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
452 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
453 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
456 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
457 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
458 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
459 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
460 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
462 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
463 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
466 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
470 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
474 I915_WRITE(ADPA, dev_priv->saveADPA);
478 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
480 I915_WRITE(LVDS, dev_priv->saveLVDS);
482 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
484 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
485 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
486 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
487 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
488 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
489 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
494 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
495 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
496 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
497 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
500 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
501 I915_WRITE(VGA0, dev_priv->saveVGA0);
502 I915_WRITE(VGA1, dev_priv->saveVGA1);
503 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
507 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
508 I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
511 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
514 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
517 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
518 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
521 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);