dev/drm/i915_suspend.c

33 #include "dev/drm/drmP.h"
34 #include "dev/drm/drm.h"
35 #include "dev/drm/i915_drm.h"
36 #include "dev/drm/i915_drv.h"
38 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
40 	struct drm_i915_private *dev_priv = dev->dev_private;
48 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
50 	struct drm_i915_private *dev_priv = dev->dev_private;
55 	if (!i915_pipe_enabled(dev, pipe))
67 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
69 	struct drm_i915_private *dev_priv = dev->dev_private;
74 	if (!i915_pipe_enabled(dev, pipe))
86 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
88 	struct drm_i915_private *dev_priv = dev->dev_private;
94 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
96 	struct drm_i915_private *dev_priv = dev->dev_private;
103 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
105 	struct drm_i915_private *dev_priv = dev->dev_private;
112 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
114 	struct drm_i915_private *dev_priv = dev->dev_private;
120 static void i915_save_vga(struct drm_device *dev)
122 	struct drm_i915_private *dev_priv = dev->dev_private;
142 	i915_write_indexed(dev, cr_index, cr_data, 0x11,
143 			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &
147 			i915_read_indexed(dev, cr_index, cr_data, i);
155 		dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
163 			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
166 		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
168 		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
170 		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
175 			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
178 static void i915_restore_vga(struct drm_device *dev)
180 	struct drm_i915_private *dev_priv = dev->dev_private;
198 		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
203 	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
205 		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
209 		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
212 	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
214 	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
216 	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
222 		i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
231 int i915_save_state(struct drm_device *dev)
233 	struct drm_i915_private *dev_priv = dev->dev_private;
237 	dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1);
239 	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
243 	if (IS_I965G(dev) && IS_MOBILE(dev))
258 	if (IS_I965G(dev))
273 	if (IS_I965G(dev)) {
277 	i915_save_palette(dev, PIPE_A);
286 	if (IS_I965G(dev))
301 	if (IS_I965GM(dev) || IS_GM45(dev)) {
305 	i915_save_palette(dev, PIPE_B);
315 	if (IS_I965G(dev))
317 	if (IS_MOBILE(dev) && !IS_I830(dev))
319 	if (!IS_I830(dev) && !IS_845G(dev))
362 	i915_save_vga(dev);
367 int i915_restore_state(struct drm_device *dev)
369 	struct drm_i915_private *dev_priv = dev->dev_private;
373 	pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1);
375 	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
379 	if (IS_I965G(dev) && IS_MOBILE(dev))
400 	if (IS_I965G(dev))
419 	if (IS_I965G(dev)) {
426 	i915_restore_palette(dev, PIPE_A);
442 	if (IS_I965G(dev))
461 	if (IS_I965G(dev)) {
468 	i915_restore_palette(dev, PIPE_B);
477 	if (IS_I965G(dev))
479 	if (IS_MOBILE(dev) && !IS_I830(dev))
481 	if (!IS_I830(dev) && !IS_845G(dev))
523 	i915_restore_vga(dev);