dev/cxgb/cxgb_sge.c

211  * HW allows up to 4 descriptors to be combined into a WR.
355 		panic("trying to coalesce %d packets in to one WR", ci.count);
1163  * 	packet.  Ethernet packets require addition of WR and CPL headers.
1260  *	write_wr_hdr_sgl - write a WR header and, optionally, SGL
1268  *	@wr_hi: top 32 bits of WR header based on WR type (big endian)
1269  *	@wr_lo: low 32 bits of WR header based on WR type (big endian)
1273  *	and we just need to write the WR header.  Otherwise we distribute the
1413 			panic("trying to coalesce %d packets in to one WR", nsegs);
2211 	from = (void *)(oh + 1);	/* Start of WR within mbuf */
3159 	uint32_t *WR, wr_hi, wr_lo, gen;
3201 		WR = (uint32_t *)txd->flit;
3202 		wr_hi = ntohl(WR[0]);
3203 		wr_lo = ntohl(WR[1]);
3210 			    WR[j], WR[j + 1], WR[j + 2], WR[j + 3]);
3226 	uint32_t *WR, wr_hi, wr_lo, gen;
3258 		WR = (uint32_t *)txd->flit;
3259 		wr_hi = ntohl(WR[0]);
3260 		wr_lo = ntohl(WR[1]);
3267 			    WR[j], WR[j + 1], WR[j + 2], WR[j + 3]);