cxgb/common/cxgb_t3_hw.c

112  *	@adap: the adapter
122 static void t3_read_indirect(adapter_t *adap, unsigned int addr_reg,
127 		t3_write_reg(adap, addr_reg, start_idx);
128 		*vals++ = t3_read_reg(adap, data_reg);
150 	adapter_t *adap = mc7->adapter;
164 			t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR,
166 			t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
167 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
169 				val = t3_read_reg(adap,
174 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
176 				val64 = t3_read_reg(adap,
250 static void mi1_init(adapter_t *adap, const struct adapter_info *ai)
252         u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
255         t3_write_reg(adap, A_MI1_CFG, val);
1412  *	@adap: the adapter
1419 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
1424 	if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1428 		t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
1429 		ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
1432 			*valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
2153 static int mac_intr_handler(adapter_t *adap, unsigned int idx)
2159 	idx = idx == 0 ? 0 : adapter_info(adap)->nports0; /* MAC idx -> port */
2160 	pi = adap2pinfo(adap, idx);
2169 	cause = (t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset)
2174 		CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx);
2178 		CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx);
2191 	    t3_read_reg(adap, A_XGM_INT_ENABLE + mac->offset)) {
2192 		t3_set_reg_field(adap, A_XGM_INT_ENABLE + mac->offset,
2201 		t3_fatal_err(adap);
2203 	t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
2300 static unsigned int calc_gpio_intr(adapter_t *adap)
2304 	for_each_port(adap, i)
2305 		if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&
2306 		    adapter_info(adap)->gpio_intr[i])
2307 			gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i];
2530 static int clear_sge_ctxt(adapter_t *adap, unsigned int id, unsigned int type)
2532 	t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
2533 	t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
2534 	t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
2535 	t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
2536 	t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff);
2537 	t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff);
2538 	t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff);
2539 	t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff);
2540 	t3_write_reg(adap, A_SG_CONTEXT_CMD,
2542 	return t3_wait_op_done(adap, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
3021  *	@adap: the adapter
3026 void t3_tp_set_offload_mode(adapter_t *adap, int enable)
3028 	if (is_offload(adap) || !enable)
3029 		t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
3035  *	@adap: the adapter
3042 static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr,
3045 	t3_write_reg(adap, A_TP_PIO_ADDR, addr);
3046 	val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
3047 	t3_write_reg(adap, A_TP_PIO_DATA, val);
3052  *	@adap: the adapter
3056 void t3_enable_filters(adapter_t *adap)
3058 	t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0);
3059 	t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN);
3060 	t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3));
3061 	tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT);
3066  *	@adap: the adapter
3070 void t3_disable_filters(adapter_t *adap)
3073 	t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_FILTEREN, 0);
3074 	t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG,
3076 	tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, F_LOOKUPEVERYPKT, 0);
3096 #define mem_region(adap, start, size, reg) \
3097 	t3_write_reg((adap), A_ ## reg, (start)); \
3102  *	@adap: the adapter
3108 static void partition_mem(adapter_t *adap, const struct tp_params *p)
3110 	unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5);
3113 	if (adap->params.rev > 0) {
3126 	t3_write_reg(adap, A_TP_PMM_SIZE,
3129 	t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
3130 	t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
3131 	t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
3132 	t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
3135 	t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
3136 	t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
3137 	t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
3143 	t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
3146 	mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR);
3147 	mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR);
3148 	t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
3150 	mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE);
3151 	mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE);
3152 	mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE);
3153 	mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE);
3156 	t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
3157 	t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
3160 	m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
3161 	    adap->params.mc5.nfilters - adap->params.mc5.nroutes;
3163 		adap->params.mc5.nservers += m - tids;
3166 static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val)
3168 	t3_write_reg(adap, A_TP_PIO_ADDR, addr);
3169 	t3_write_reg(adap, A_TP_PIO_DATA, val);
3172 static inline u32 tp_rd_indirect(adapter_t *adap, unsigned int addr)
3174 	t3_write_reg(adap, A_TP_PIO_ADDR, addr);
3175 	return t3_read_reg(adap, A_TP_PIO_DATA);
3178 static void tp_config(adapter_t *adap, const struct tp_params *p)
3180 	t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
3183 	t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
3186 	t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
3190 	t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
3192 	t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
3193 	t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
3194 	t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
3195 			 adap->params.rev > 0 ? F_ENABLEESND :
3197 	t3_set_reg_field(adap, A_TP_PC_CONFIG,
3201 	t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
3204 	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
3205 	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
3207 	if (adap->params.rev > 0) {
3208 		tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
3209 		t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
3211 		t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
3212 		tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50);
3213 		tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688);
3214 		tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688);
3216 		t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
3218 	if (adap->params.rev == T3_REV_C)
3219 		t3_set_reg_field(adap, A_TP_PC_CONFIG,
3223 	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
3224 	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
3225 	t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
3226 	t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
3228 	if (adap->params.nports > 2) {
3229 		t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0,
3232 		tp_wr_bits_indirect(adap, A_TP_QOS_RX_MAP_MODE,
3234 		tp_wr_indirect(adap, A_TP_INGRESS_CONFIG, V_BITPOS0(48) |
3238 		tp_wr_indirect(adap, A_TP_PREAMBLE_MSB, 0xfb000000);
3239 		tp_wr_indirect(adap, A_TP_PREAMBLE_LSB, 0xd5);
3240 		tp_wr_indirect(adap, A_TP_INTF_FROM_TX_PKT, F_INTFFROMTXPKT);
3250  *	@adap: the adapter to set
3256 static void tp_set_timers(adapter_t *adap, unsigned int core_clk)
3258 	unsigned int tre = adap->params.tp.tre;
3259 	unsigned int dack_re = adap->params.tp.dack_re;
3263 	t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
3266 	t3_write_reg(adap, A_TP_DACK_TIMER,
3268 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
3269 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
3270 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
3271 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
3272 	t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
3279 	t3_write_reg(adap, A_TP_MSL,
3280 		     adap->params.rev > 0 ? 0 : 2 SECONDS);
3281 	t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
3282 	t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
3283 	t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
3284 	t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
3285 	t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
3286 	t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
3287 	t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
3288 	t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
3295  *	@adap: the adapter
3301 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh)
3308 	val = t3_read_reg(adap, A_TP_PARA_REG3);
3316 		t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
3319 	t3_write_reg(adap, A_TP_PARA_REG3, val);
3325  *	@adap: the adapter
3331 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size)
3333 	t3_write_reg(adap, A_TP_PARA_REG7,
3411  *	@adap: the adapter
3421 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
3438 		t3_write_reg(adap, A_TP_MTU_TABLE,
3447 			t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
3455  *	@adap: the adapter
3460 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS])
3467 		t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i);
3468 		val = t3_read_reg(adap, A_TP_MTU_TABLE);
3475  *	@adap: the adapter
3481 void t3_get_cong_cntl_tab(adapter_t *adap,
3488 			t3_write_reg(adap, A_TP_CCTRL_TABLE,
3490 			incr[mtu][w] = (unsigned short)t3_read_reg(adap,
3497  *	@adap: the adapter
3502 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps)
3504 	t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *)tps,
3510  *	@adap: the adapter
3515 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED])
3517 	unsigned int i, tick_ns = dack_ticks_to_usec(adap, 1000);
3520 		t3_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
3521 		pace_vals[i] = t3_read_reg(adap, A_TP_PACE_TABLE) * tick_ns;
3527  *	@adap: the adapter
3534 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
3537 	unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
3540 		t3_write_reg(adap, A_TP_PACE_TABLE, (start << 16) |
3544 #define ulp_region(adap, name, start, len) \
3545 	t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
3546 	t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
3550 #define ulptx_region(adap, name, start, len) \
3551 	t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
3552 	t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
3555 static void ulp_config(adapter_t *adap, const struct tp_params *p)
3559 	ulp_region(adap, ISCSI, m, p->chan_rx_size / 8);
3560 	ulp_region(adap, TDDP, m, p->chan_rx_size / 8);
3561 	ulptx_region(adap, TPT, m, p->chan_rx_size / 4);
3562 	ulp_region(adap, STAG, m, p->chan_rx_size / 4);
3563 	ulp_region(adap, RQ, m, p->chan_rx_size / 4);
3564 	ulptx_region(adap, PBL, m, p->chan_rx_size / 4);
3565 	ulp_region(adap, PBL, m, p->chan_rx_size / 4);
3566 	t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
3577 int t3_set_proto_sram(adapter_t *adap, const u8 *data)
3583 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
3584 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
3585 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
3586 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
3587 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
3589 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
3590 		if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
3685  *	@adap: the adapter
3691 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched)
3694 	unsigned int clk = adap->params.vpd.cclk * 1000;
3716 	t3_write_reg(adap, A_TP_TM_PIO_ADDR,
3718 	v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3723 	t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3729  *	@adap: the adapter
3735 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg)
3740 	ipg *= core_ticks_per_usec(adap);
3745 	t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3746 	v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3751 	t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3752 	t3_read_reg(adap, A_TP_TM_PIO_DATA);
3758  *	@adap: the adapter
3765 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
3772 		t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3773 		v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3781 			v = (adap->params.vpd.cclk * 1000) / cpt;
3787 		t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3788 		v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3792 		*ipg = (10000 * v) / core_ticks_per_usec(adap);
3798  *	@adap: the adapter
3803 static int tp_init(adapter_t *adap, const struct tp_params *p)
3807 	tp_config(adap, p);
3808 	t3_set_vlan_accel(adap, 3, 0);
3810 	if (is_offload(adap)) {
3811 		tp_set_timers(adap, adap->params.vpd.cclk * 1000);
3812 		t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
3813 		busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE,
3816 			CH_ERR(adap, "TP initialization timed out\n");
3820 		t3_write_reg(adap, A_TP_RESET, F_TPRESET);
3826  *	@adap: the adapter
3831 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask)
3833 	if (port_mask & ~((1 << adap->params.nports) - 1))
3835 	t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
3842  *	@adap: the adapter
3848 static void chan_init_hw(adapter_t *adap, unsigned int chan_map)
3853 		t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
3854 		t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
3855 		t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT |
3858 		t3_write_reg(adap, A_PM1_TX_CFG,
3861 			t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3863 		t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xd9c8);
3864 		t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfbea);
3866 		t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
3867 		t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
3868 		t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
3870 		t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
3873 		t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
3874 		t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
3875 		t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3878 			t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
3880 		t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xba98);
3881 		t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfedc);
4067 static void config_pcie(adapter_t *adap)
4086 	t3_os_pci_read_config_2(adap,
4087 				adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
4095 	t3_os_pci_read_config_2(adap, 0x2, &devid);
4097 		t3_os_pci_write_config_2(adap,
4098 		    adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
4103 	t3_os_pci_read_config_2(adap,
4104 				adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
4107 	fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
4108 	fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
4109 			G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
4110 	log2_width = fls(adap->params.pci.width) - 1;
4116 	if (adap->params.rev == 0)
4117 		t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
4121 		t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
4124 	t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
4127 	t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
4128 	t3_set_reg_field(adap, A_PCIE_CFG, 0,
4421 static int init_parity(adapter_t *adap)
4425 	if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
4429 		err = clear_sge_ctxt(adap, i, F_EGRESS);
4431 		err = clear_sge_ctxt(adap, i, F_EGRESS);
4433 		err = clear_sge_ctxt(adap, i, F_RESPONSEQ);
4437 	t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);
4440 			t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |
4443 			err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG,
4607 int t3_reinit_adapter(adapter_t *adap)
4612 	early_hw_init(adap, adap->params.info);
4613 	ret = init_parity(adap);
4617 	if (adap->params.nports > 2 &&
4618 	    (ret = t3_vsc7323_init(adap, adap->params.nports)))
4621 	for_each_port(adap, i) {
4623 		struct port_info *p = adap2pinfo(adap, i);
4626 			unsigned port_type = adap->params.vpd.port_type[j];
4635 			if (j >= ARRAY_SIZE(adap->params.vpd.port_type))