dev/bxe/bxe.c

1511               struct dmae_cmd *dmae,
1519         REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1575                         struct dmae_cmd *dmae,
1579     memset(dmae, 0, sizeof(struct dmae_cmd));
1582     dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1586     dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1587     dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1588     dmae->comp_val     = DMAE_COMP_VAL;
1594                          struct dmae_cmd *dmae)
1605     bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1640     struct dmae_cmd dmae;
1659     bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1662     dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1663     dmae.src_addr_hi = 0;
1664     dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1665     dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1666     dmae.len         = len32;
1669     if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1680     struct dmae_cmd dmae;
1696     bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1699     dmae.src_addr_lo = U64_LO(dma_addr);
1700     dmae.src_addr_hi = U64_HI(dma_addr);
1701     dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1702     dmae.dst_addr_hi = 0;
1703     dmae.len         = len32;
1706     if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
11022      * respond. The write queue in PGLUE would stuck, dmae commands
15548              * use rd/wr since we cannot use dmae. This is safe
17244  *          dmae-operations (writing to pram for example.)
17634      * common phase, we need to enable it here before any dmae access are