dev/bxe/bxe.c

1204     /* enable both bits, even on read */
1307     /* enable access to nvram interface */
1412     /* enable access to nvram interface */
1476     /* enable access to nvram interface */
2235                      uint8_t          enable)
2237     REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2238     REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2239     REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2240     REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable);
3683     /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
3857      * PMF probably in the middle of TX disable/enable transaction
3860      * 3. Wait, that TX disable/enable transaction completes
3988      * enable further HW_RESET transaction.
4100      * PMF probably in the middle of TX disable/enable transaction
4601         /* toggle the LRO capabilites enable flag */
4609         /* toggle the TXCSUM checksum capabilites enable flag */
4626         /* toggle the RXCSUM checksum capabilities enable flag */
4672         /* toggle VLAN_MTU capabilities enable flag */
7858     /* enable nig attention */
10149         /* get VN min rate and enable fairness if not 0 */
10159         /* always enable rate shaping and fairness */
10339                 /* enable nig and gpio3 attention */
10404             /* enable nig and gpio3 attention */
11143      * re-enable attentions
13770     /* get the override preemphasis flag and enable it or turn it off */
15860 /* must be called after sriov-enable */
16325     /* enable bus master capability */
17032     /* enable interrupt to signal the IGU */
17092         /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
17141          * 4-port mode or 2-port mode we need to turn off master-enable for
17156             /* clear pf enable */
17169          * enable HW interrupt from PXP on USDM overflow
17243  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
17257  *      c.  PF enable in the PGLC.
17260  *      e.  PF enable in the CFC (WEAK + STRONG)
17261  *      f.  Timers scan enable
17265  *      c.  Clear the PF enable bit in the PXP.
17266  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
17278  *      there is no Timer disable during Func6/7 enable. This is because the
17380         /* enable hw interrupt from doorbell Q */
17494     /* enable context validation interrupt from CFC */
17634      * common phase, we need to enable it here before any dmae access are
17635      * attempted. Therefore we manually added the enable-master to the
17798         /* 0x2 disable mf_ov, 0x1 enable */
17822     /* If SPIO5 is set to generate interrupts, enable it for this port */
18152     /* Re-enable PF target read access */
18185      * Master enable - Due to WB DMAE writes performed before this
18263          * Master enable - Due to WB DMAE writes performed before this
19047      * will re-enable parity attentions right after the dump.