Lines Matching refs:REG_RD_IND
1222 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1225 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
4152 val = REG_RD_IND(sc, cpu_reg->mode);
4175 val = REG_RD_IND(sc, cpu_reg->mode);
8347 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8958 val = REG_RD_IND(sc, result);
10334 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10335 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10343 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10344 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10406 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10407 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10424 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10425 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10433 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10434 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10442 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10443 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10451 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10452 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10460 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10461 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10480 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10481 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10489 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10490 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
11039 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11043 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11047 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11051 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11055 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11059 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11215 fw_version[i] = htonl(REG_RD_IND(sc,
11219 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11223 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11227 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11242 REG_RD_IND(sc, i),
11243 REG_RD_IND(sc, i + 0x4),
11244 REG_RD_IND(sc, i + 0x8),
11245 REG_RD_IND(sc, i + 0xC));
11274 fw_version[i] = htonl(REG_RD_IND(sc,
11279 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11283 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11287 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11302 REG_RD_IND(sc, i),
11303 REG_RD_IND(sc, i + 0x4),
11304 REG_RD_IND(sc, i + 0x8),
11305 REG_RD_IND(sc, i + 0xC));
11334 fw_version[i] = htonl(REG_RD_IND(sc,
11339 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11343 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11347 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11362 REG_RD_IND(sc, i),
11363 REG_RD_IND(sc, i + 0x4),
11364 REG_RD_IND(sc, i + 0x8),
11365 REG_RD_IND(sc, i + 0xC));
11394 fw_version[i] = htonl(REG_RD_IND(sc,
11399 val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11403 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11407 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11422 REG_RD_IND(sc, i),
11423 REG_RD_IND(sc, i + 0x4),
11424 REG_RD_IND(sc, i + 0x8),
11425 REG_RD_IND(sc, i + 0xC));
11454 fw_version[i] = htonl(REG_RD_IND(sc,
11459 val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11463 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11467 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11480 REG_RD_IND(sc, i),
11481 REG_RD_IND(sc, i + 0x4),
11482 REG_RD_IND(sc, i + 0x8),
11483 REG_RD_IND(sc, i + 0xC));
11511 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11518 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11519 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11526 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11527 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11533 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11540 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11549 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);