Lines Matching refs:val
1069 u32 val;
1222 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1223 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1234 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1238 num = (u8) (val >> (24 - (i * 8)));
1251 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1252 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1257 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1258 if (val & BCE_CONDITION_MFW_RUN_MASK)
1264 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1265 val &= BCE_CONDITION_MFW_RUN_MASK;
1266 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1267 (val != BCE_CONDITION_MFW_RUN_NONE)) {
1273 val = bce_reg_rd_ind(sc, addr + j * 4);
1274 val = bswap32(val);
1275 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1289 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1290 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1324 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1330 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1645 u32 val = REG_RD(sc, offset);
1646 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1647 __FUNCTION__, offset, val);
1648 return val;
1659 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1661 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1662 __FUNCTION__, offset, val);
1663 REG_WR16(sc, offset, val);
1674 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1676 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1677 __FUNCTION__, offset, val);
1678 REG_WR(sc, offset, val);
1701 u32 val;
1702 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1703 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1704 __FUNCTION__, offset, val);
1705 return val;
1724 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1729 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1730 __FUNCTION__, offset, val);
1733 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1746 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1749 "0x%08X\n", __FUNCTION__, val, offset);
1751 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1766 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1769 "0x%08X\n", __FUNCTION__, val, offset);
1771 return val;
1788 u32 idx, offset, retry_cnt = 5, val;
1801 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1802 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1807 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1812 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1815 val = REG_RD(sc, BCE_CTX_DATA);
1819 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1821 return(val);
1839 u32 val, retry_cnt = 5;
1842 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1854 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1855 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1860 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1884 u32 val;
1900 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1901 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1903 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1910 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1913 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1918 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1919 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1922 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1923 val &= BCE_EMAC_MDIO_COMM_DATA;
1929 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1932 val = 0x0;
1934 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1939 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1940 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1942 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1948 DB_PRINT_PHY_REG(reg, val);
1949 return (val & 0xffff);
1962 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1970 DB_PRINT_PHY_REG(reg, val);
1992 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
2040 int media_active, media_status, val;
2062 val = REG_RD(sc, BCE_EMAC_MODE);
2063 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2073 val |= BCE_EMAC_MODE_PORT_MII_10;
2079 val |= BCE_EMAC_MODE_PORT_MII;
2083 val |= BCE_EMAC_MODE_25G;
2088 val |= BCE_EMAC_MODE_PORT_GMII;
2093 val |= BCE_EMAC_MODE_PORT_GMII;
2100 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2105 REG_WR(sc, BCE_EMAC_MODE, val);
2151 u32 val;
2159 val = REG_RD(sc, BCE_NVM_SW_ARB);
2160 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2189 u32 val;
2200 val = REG_RD(sc, BCE_NVM_SW_ARB);
2201 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2229 u32 val;
2234 val = REG_RD(sc, BCE_MISC_CFG);
2235 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2246 val = REG_RD(sc, BCE_NVM_COMMAND);
2247 if (val & BCE_NVM_COMMAND_DONE)
2274 u32 val;
2278 val = REG_RD(sc, BCE_MISC_CFG);
2279 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2299 u32 val;
2303 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2305 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2323 u32 val;
2327 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2330 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2373 u32 val;
2377 val = REG_RD(sc, BCE_NVM_COMMAND);
2378 if (val & BCE_NVM_COMMAND_DONE)
2432 u32 val;
2436 val = REG_RD(sc, BCE_NVM_COMMAND);
2437 if (val & BCE_NVM_COMMAND_DONE) {
2438 val = REG_RD(sc, BCE_NVM_READ);
2440 val = bce_be32toh(val);
2441 memcpy(ret_val, &val, 4);
2470 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2493 memcpy(&val32, val, 4);
2530 u32 val;
2542 val = REG_RD(sc, BCE_NVM_CFG1);
2553 if (val & 0x40000000) {
2561 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2574 if (val & (1 << 23))
2583 if ((val & mask) == (flash->strapping & mask)) {
2616 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2617 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2618 if (val)
2619 sc->bce_flash_size = val;
3094 u32 val;
3102 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3103 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3121 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3122 strap = (val &
3125 strap = (val &
3172 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3173 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3959 u32 val;
3982 val = bce_shmem_rd(sc, BCE_FW_MB);
3983 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3989 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
4021 u32 val;
4037 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4038 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4041 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4042 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4147 u32 val;
4152 val = REG_RD_IND(sc, cpu_reg->mode);
4153 val &= ~cpu_reg->mode_value_halt;
4155 REG_WR_IND(sc, cpu_reg->mode, val);
4170 u32 val;
4175 val = REG_RD_IND(sc, cpu_reg->mode);
4176 val |= cpu_reg->mode_value_halt;
4177 REG_WR_IND(sc, cpu_reg->mode, val);
4758 u32 offset, val, vcid_addr;
4774 val = BCE_CTX_COMMAND_ENABLED |
4776 val |= (BCM_PAGE_BITS - 8) << 16;
4777 REG_WR(sc, BCE_CTX_COMMAND, val);
4781 val = REG_RD(sc, BCE_CTX_COMMAND);
4782 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4786 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4805 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4806 if ((val &
4811 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4903 u32 val;
4912 val = (mac_addr[0] << 8) | mac_addr[1];
4914 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4916 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4919 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4973 u32 emac_mode_save, val;
4998 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
5003 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5004 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5005 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5021 val = REG_RD(sc, BCE_MISC_ID);
5029 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5032 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5034 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5037 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5041 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5042 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5050 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5060 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5061 if (val != 0x01020304) {
5083 val = REG_RD(sc, BCE_EMAC_MODE);
5084 val = (val & ~emac_mode_mask) | emac_mode_save;
5085 REG_WR(sc, BCE_EMAC_MODE, val);
5096 u32 val;
5107 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5116 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5119 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5129 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5131 REG_WR(sc, BCE_DMA_CONFIG, val);
5148 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5149 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5157 val = REG_RD(sc, BCE_MQ_CONFIG);
5158 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5159 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5163 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5165 val |= BCE_MQ_CONFIG_HALT_DIS;
5168 REG_WR(sc, BCE_MQ_CONFIG, val);
5170 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5171 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5172 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5175 val = (BCM_PAGE_BITS - 8) << 24;
5176 REG_WR(sc, BCE_RV2P_CONFIG, val);
5179 val = REG_RD(sc, BCE_TBDR_CONFIG);
5180 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5181 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5182 REG_WR(sc, BCE_TBDR_CONFIG, val);
5203 u32 reg, val;
5212 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
5215 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5259 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5280 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5289 val |= BCE_HC_CONFIG_ONE_SHOT;
5293 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5296 REG_WR(sc, BCE_HC_CONFIG, val);
5321 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5322 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5323 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5338 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5340 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5592 u32 val;
5599 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5601 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5602 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5604 BCE_L2CTX_TX_CMD_TYPE_XI, val);
5607 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5609 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5610 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5612 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5615 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5616 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5617 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5618 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5621 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5623 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5624 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5626 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5744 u32 val;
5749 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5787 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5791 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5795 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5796 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5800 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5801 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5802 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5803 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5976 u32 val;
6015 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
6016 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6023 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6024 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6025 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6026 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
8918 u32 val[1];
8919 u8 *data = (u8 *) val;
8928 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8946 u32 val, result;
8955 val = REG_RD(sc, result);
8956 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8958 val = REG_RD_IND(sc, result);
8959 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8979 u16 val;
8990 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8991 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
9689 u32 val;
9690 val = REG_RD(sc, BCE_MISC_COMMAND);
9691 val |= BCE_MISC_COMMAND_DISABLE_ALL;
9692 REG_WR(sc, BCE_MISC_COMMAND, val);
9706 u32 val;
9707 val = REG_RD(sc, BCE_MISC_COMMAND);
9708 val |= BCE_MISC_COMMAND_ENABLE_ALL;
9709 REG_WR(sc, BCE_MISC_COMMAND, val);
10287 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10300 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10304 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10306 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) |
10310 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10312 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) |
10316 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10318 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
10322 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10469 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
10474 val = val |
10477 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10984 u32 val;
10993 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10995 val, BCE_MISC_ENABLE_STATUS_BITS);
10997 val = REG_RD(sc, BCE_DMA_STATUS);
10999 val, BCE_DMA_STATUS);
11001 val = REG_RD(sc, BCE_CTX_STATUS);
11003 val, BCE_CTX_STATUS);
11005 val = REG_RD(sc, BCE_EMAC_STATUS);
11007 val, BCE_EMAC_STATUS);
11009 val = REG_RD(sc, BCE_RPM_STATUS);
11011 val, BCE_RPM_STATUS);
11014 val = REG_RD(sc, 0x2004);
11016 val, 0x2004);
11018 val = REG_RD(sc, BCE_RV2P_STATUS);
11020 val, BCE_RV2P_STATUS);
11023 val = REG_RD(sc, 0x2c04);
11025 val, 0x2c04);
11027 val = REG_RD(sc, BCE_TBDR_STATUS);
11029 val, BCE_TBDR_STATUS);
11031 val = REG_RD(sc, BCE_TDMA_STATUS);
11033 val, BCE_TDMA_STATUS);
11035 val = REG_RD(sc, BCE_HC_STATUS);
11037 val, BCE_HC_STATUS);
11039 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11041 val, BCE_TXP_CPU_STATE);
11043 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11045 val, BCE_TPAT_CPU_STATE);
11047 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11049 val, BCE_RXP_CPU_STATE);
11051 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11053 val, BCE_COM_CPU_STATE);
11055 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11057 val, BCE_MCP_CPU_STATE);
11059 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11061 val, BCE_CP_CPU_STATE);
11165 u32 val;
11174 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11176 val, BCE_BC_RESET_TYPE);
11178 val = bce_shmem_rd(sc, BCE_BC_STATE);
11180 val, BCE_BC_STATE);
11182 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11184 val, BCE_BC_STATE_CONDITION);
11186 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11188 val, BCE_BC_STATE_DEBUG_CMD);
11206 u32 val;
11219 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11221 val, BCE_TXP_CPU_MODE);
11223 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11225 val, BCE_TXP_CPU_STATE);
11227 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11229 val, BCE_TXP_CPU_EVENT_MASK);
11265 u32 val;
11279 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11281 val, BCE_RXP_CPU_MODE);
11283 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11285 val, BCE_RXP_CPU_STATE);
11287 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11289 val, BCE_RXP_CPU_EVENT_MASK);
11325 u32 val;
11339 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11341 val, BCE_TPAT_CPU_MODE);
11343 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11345 val, BCE_TPAT_CPU_STATE);
11347 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11349 val, BCE_TPAT_CPU_EVENT_MASK);
11385 u32 val;
11399 val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11401 val, BCE_CP_CPU_MODE);
11403 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11405 val, BCE_CP_CPU_STATE);
11407 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11408 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11445 u32 val;
11459 val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11461 val, BCE_COM_CPU_MODE);
11463 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11465 val, BCE_COM_CPU_STATE);
11467 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11468 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11503 u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11511 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11512 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11513 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11516 val = 0x00000001;
11517 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11524 val = 0x00000001;
11525 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11533 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11534 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11535 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11538 val = 0x68007800;
11539 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11540 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11541 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11542 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11547 val = 0x68007800;
11548 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11549 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11550 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11551 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;