ath_hal/ar9002/ar9287_reset.c

22 #include "ah.h"
45 ar9287SetPowerCalTable(struct ath_hal *ah,
55 	HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
64 		pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5),
72 		AH5416(ah)->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
87 	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
89 	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
91 	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
93 	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
103 				ar9287olcGetTxGainIndex(ah, chan,
107 				ar9287olcSetPDADCs(ah, txPower, i);
127 ar9287SetPowerPerRateTable(struct ath_hal *ah,
162 	ar5416GetChannelCenters(ah,  chan, &centers);
173 	ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);
183 	switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {
202 		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPowerCck,
204 		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower2G,
206 		ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower2GHT20,
212 			ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower2GHT40,
215 			ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPowerCck,
217 			ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower2G,
252 							rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
304 	ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray,
328 ar9287SetTransmitPower(struct ath_hal *ah,
335 	struct ath_hal_5212 *ahp = AH5212(ah);
344 	HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
347 	AH5416(ah)->ah_ht40PowerIncForPdadc = 2;
350 	OS_MEMZERO(AH5416(ah)->ah_ratesArray,
351 	  sizeof(AH5416(ah)->ah_ratesArray));
352 	cfgCtl = ath_hal_getctl(ah, chan);
356 	    AH_PRIVATE(ah)->ah_powerLimit);
358 	HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
362 	AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
365 	if (! ar9287SetPowerPerRateTable(ah, pEepData,  chan,
366 	    &AH5416(ah)->ah_ratesArray[0],
370 		HALDEBUG(ah, HAL_DEBUG_ANY,
376 	ar9287SetPowerCalTable(ah, chan, &txPowerIndexOffset);
379 	maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb],
380 	    AH5416(ah)->ah_ratesArray[rateHt20_0]);
382 	    AH5416(ah)->ah_ratesArray[rate1l]);
386 		    AH5416(ah)->ah_ratesArray[rateHt40_0]);
389 	AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
397 	for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) {
398 		AH5416(ah)->ah_ratesArray[i] =
400 		      AH5416(ah)->ah_ratesArray[i]);
402 		AH5416(ah)->ah_ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
403 		if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER)
404 			AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER;
405 		if (AH5416(ah)->ah_ratesArray[i] < 0)
406 			AH5416(ah)->ah_ratesArray[i] = 0;
410 	ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray);
421 		AH5416(ah)->ah_ratesArray[rateHt40_0] +=
422 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
423 		AH5416(ah)->ah_ratesArray[rateHt40_1] +=
424 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
425 		AH5416(ah)->ah_ratesArray[rateHt40_2] +=
426 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
427 		AH5416(ah)->ah_ratesArray[rateHt40_3] +=
428 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
429 		AH5416(ah)->ah_ratesArray[rateHt40_4] +=
430 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
431 		AH5416(ah)->ah_ratesArray[rateHt40_5] +=
432 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
433 		AH5416(ah)->ah_ratesArray[rateHt40_6] +=
434 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
435 		AH5416(ah)->ah_ratesArray[rateHt40_7] +=
436 		  AH5416(ah)->ah_ht40PowerIncForPdadc;
440 	ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray);
452 ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
454 	const HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
486 	OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
491 		OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
494 		OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset,
495 			  (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)
506 		OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
509 		OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
512 		OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
515 		OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
521 		OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
524 		OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
527 	OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
530 	OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
536 	OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
539 	OS_REG_RMW_FIELD(ah, AR_PHY_CCA,
541 	OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
544 	regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH0);
559 	OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);
561 	regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH1);
575 	OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);
577 	OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
579 	OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
582 	OS_A_REG_RMW_FIELD(ah, AR9287_AN_TOP2,