ath_hal/ar9002/ar9287_attach.c

21 #include "ah.h"
68 static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
70 static void ar9287DisablePCIE(struct ath_hal *ah);
71 static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah);
72 static void ar9287WriteIni(struct ath_hal *ah,
76 ar9287AniSetup(struct ath_hal *ah)
102 	AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;
105         ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
119 	struct ath_hal *ah;
137 	ah = &ahp->ah_priv.h;
139 	ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
142 		AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
143 		AH_PRIVATE(ah)->ah_eepromWrite = NULL;
144 		ah->ah_eepromdata = eepromdata;
150 	AH5416(ah)->ah_initPLL = ar9280InitPLL;
152 	ah->ah_setAntennaSwitch		= ar9287SetAntennaSwitch;
153 	ah->ah_configPCIE		= ar9287ConfigPCIE;
154 	ah->ah_disablePCIE		= ar9287DisablePCIE;
156 	AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;
157 	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;
158 	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;
159 	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;
161 	AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;
163 	AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;
164 	AH5416(ah)->ah_writeIni		= ar9287WriteIni;
166 	ah->ah_setTxPower		= ar9287SetTransmitPower;
167 	ah->ah_setBoardValues		= ar9287SetBoardValues;
169 	AH5416(ah)->ah_olcInit		= ar9287olcInit;
170 	AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;
171 	//AH5416(ah)->ah_setPowerCalTable	= ar9287SetPowerCalTable;
172 	AH5416(ah)->ah_cal_initcal	= ar9287InitCalHardware;
173 	AH5416(ah)->ah_cal_pacal	= ar9287PACal;
179 	AH5416(ah)->ah_rx_chainmask	= AR9287_DEFAULT_RXCHAINMASK;
180 	AH5416(ah)->ah_tx_chainmask	= AR9287_DEFAULT_TXCHAINMASK;
182 	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
184 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
190 	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
191 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
197 	val = OS_REG_READ(ah, AR_SREV);
198 	HALDEBUG(ah, HAL_DEBUG_ATTACH,
203 	AH_PRIVATE(ah)->ah_macVersion =
205 	AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
206 	AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
209 	if (! AR_SREV_KIWI_12_OR_LATER(ah)) {
210 		ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");
220 	HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
227 	HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
237 	ar5416AttachPCIE(ah);
239 	ecode = ath_hal_9287EepromAttach(ah);
243 	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
244 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
249 	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
251 	if (!ar5212ChipTest(ah)) {
252 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
262 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
265 	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
266 	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
271 		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
272 			AH_PRIVATE(ah)->ah_analog5GhzRev =
277 		HALDEBUG(ah, HAL_DEBUG_ANY,
280 		    AH_PRIVATE(ah)->ah_analog5GhzRev);
285 	rfStatus = ar9287RfAttach(ah, &ecode);
287 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
296 	if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
297 		ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
307 	(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
309 		ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
321 	if (!ar9287FillCapabilityInfo(ah)) {
326 	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
328 		HALDEBUG(ah, HAL_DEBUG_ANY,
334 	AH_PRIVATE(ah)->ah_currentRD =
335 	    ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
336 	AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;
345 		OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
347 	ar9287AniSetup(ah);			/* Anti Noise Immunity */
350 	AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
351 	AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
352 	AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
353 	AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;
354 	AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;
355 	AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;
357 	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
359 	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
361 	return ah;
363 	if (ah != AH_NULL)
364 		ah->ah_detach(ah);
371 ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
373 	if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
374 		ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
376 		OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
378 		OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
383 ar9287DisablePCIE(struct ath_hal *ah)
389 ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
414 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
415 	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
417 	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);
418 	regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);
419 	regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);
420 	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);
429 ar9287FillCapabilityInfo(struct ath_hal *ah)
431 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
433 	if (!ar5416FillCapabilityInfo(ah))
478 ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)