Lines Matching refs:ah
27 #include "ah.h"
54 static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah,
60 static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah,
64 static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
72 ar9285SetTransmitPower(struct ath_hal *ah,
79 struct ath_hal_5212 *ahp = AH5212(ah);
88 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
91 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
93 AH5416(ah)->ah_ht40PowerIncForPdadc = 2;
96 OS_MEMZERO(AH5416(ah)->ah_ratesArray, sizeof(AH5416(ah)->ah_ratesArray));
97 cfgCtl = ath_hal_getctl(ah, chan);
100 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
102 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
105 if (IS_EEP_MINOR_V2(ah)) {
106 AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
109 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan,
110 &AH5416(ah)->ah_ratesArray[0],cfgCtl,
113 HALDEBUG(ah, HAL_DEBUG_ANY,
118 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
119 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
124 maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb],
125 AH5416(ah)->ah_ratesArray[rateHt20_0]);
126 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rate1l]);
129 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rateHt40_0]);
133 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
140 for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) {
141 AH5416(ah)->ah_ratesArray[i] = (int16_t)(txPowerIndexOffset + AH5416(ah)->ah_ratesArray[i]);
143 AH5416(ah)->ah_ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
144 if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER)
145 AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER;
146 if (AH5416(ah)->ah_ratesArray[i] < 0)
147 AH5416(ah)->ah_ratesArray[i] = 0;
151 ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray);
162 AH5416(ah)->ah_ratesArray[rateHt40_0] +=
163 AH5416(ah)->ah_ht40PowerIncForPdadc;
164 AH5416(ah)->ah_ratesArray[rateHt40_1] +=
165 AH5416(ah)->ah_ht40PowerIncForPdadc;
166 AH5416(ah)->ah_ratesArray[rateHt40_2] +=
167 AH5416(ah)->ah_ht40PowerIncForPdadc;
168 AH5416(ah)->ah_ratesArray[rateHt40_3] +=
169 AH5416(ah)->ah_ht40PowerIncForPdadc;
170 AH5416(ah)->ah_ratesArray[rateHt40_4] +=
171 AH5416(ah)->ah_ht40PowerIncForPdadc;
172 AH5416(ah)->ah_ratesArray[rateHt40_5] +=
173 AH5416(ah)->ah_ht40PowerIncForPdadc;
174 AH5416(ah)->ah_ratesArray[rateHt40_6] +=
175 AH5416(ah)->ah_ht40PowerIncForPdadc;
176 AH5416(ah)->ah_ratesArray[rateHt40_7] +=
177 AH5416(ah)->ah_ht40PowerIncForPdadc;
181 ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray);
189 ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal,
192 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
195 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0),
196 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) &
206 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
208 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
210 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
212 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
216 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
219 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
221 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
224 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
228 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
230 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
233 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
235 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
244 ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
246 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
255 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
258 ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal);
261 (void) ar9285SetAntennaSwitch(ah, AH5212(ah)->ah_antControl);
299 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]);
300 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]);
301 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]);
302 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]);
303 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]);
305 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]);
306 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]);
307 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]);
308 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]);
309 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]);
311 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]);
312 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]);
313 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]);
314 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]);
315 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]);
317 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
319 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
322 OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
328 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
331 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
333 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
338 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,
340 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,
347 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
362 if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) {
365 ath_hal_printf(ah, "[ath]: adjusting cck tx gain factor\n");
371 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
372 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
373 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
378 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
383 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
384 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
396 ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
426 ar5416GetChannelCenters(ah, chan, ¢ers);
434 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);
447 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
449 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
451 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
457 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
460 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
462 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
497 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], AH_TRUE);
547 ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray,
564 ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
582 if (IS_EEP_MINOR_V2(ah)) {
585 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
605 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues);
608 regChainOffset = ar5416GetRegChainOffset(ah, i);
612 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
618 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
624 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries);
628 ar5416WritePdadcValues(ah, i, pdadcValues);
637 ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
668 ar5416GetChannelCenters(ah, chan, ¢ers);
732 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) {
747 if (AR_SREV_MERLIN_20_OR_LATER(ah))