Lines Matching refs:regVal

64 	int regVal;
86 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
87 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
91 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL);
96 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
97 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
98 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);
99 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
105 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
106 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
107 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_ALT_GAINTB);
108 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
114 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
115 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
116 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_ALT_GAINTB);
117 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
121 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
122 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
123 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
124 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
126 regVal |= SM((ant_div_control1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
128 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
129 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
146 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
147 regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | AR_PHY_9285_ANT_DIV_ALT_LNACONF));
148 regVal |= (HAL_ANT_DIV_COMB_LNA1 << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S);
149 regVal |= (HAL_ANT_DIV_COMB_LNA2 << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S);
150 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS));
151 regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S);
152 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);