Lines Matching refs:ah
21 #include "ah.h"
69 static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
71 static void ar9285DisablePCIE(struct ath_hal *ah);
72 static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
73 static void ar9285WriteIni(struct ath_hal *ah,
77 ar9285AniSetup(struct ath_hal *ah)
103 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
105 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
116 ar9285_eeprom_print_diversity_settings(struct ath_hal *ah)
118 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
121 ath_hal_printf(ah, "[ath] AR9285 Main LNA config: %s\n",
123 ath_hal_printf(ah, "[ath] AR9285 Alt LNA config: %s\n",
125 ath_hal_printf(ah, "[ath] LNA diversity %s, Diversity %s\n",
141 struct ath_hal *ah;
158 ah = &ahp->ah_priv.h;
160 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
169 AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
170 AH_PRIVATE(ah)->ah_eepromWrite = NULL;
171 ah->ah_eepromdata = eepromdata;
175 AH5416(ah)->ah_initPLL = ar9280InitPLL;
176 AH5416(ah)->ah_btCoexSetDiversity = ar9285BTCoexAntennaDiversity;
178 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
179 ah->ah_configPCIE = ar9285ConfigPCIE;
180 ah->ah_disablePCIE = ar9285DisablePCIE;
181 ah->ah_setTxPower = ar9285SetTransmitPower;
182 ah->ah_setBoardValues = ar9285SetBoardValues;
183 ah->ah_btCoexSetParameter = ar9285BTCoexSetParameter;
184 ah->ah_divLnaConfGet = ar9285_antdiv_comb_conf_get;
185 ah->ah_divLnaConfSet = ar9285_antdiv_comb_conf_set;
187 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
188 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
189 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
190 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
191 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
193 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
194 AH5416(ah)->ah_writeIni = ar9285WriteIni;
195 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
196 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
200 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
202 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
208 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
209 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
215 val = OS_REG_READ(ah, AR_SREV);
216 HALDEBUG(ah, HAL_DEBUG_ATTACH,
221 AH_PRIVATE(ah)->ah_macVersion =
223 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
224 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
227 if (AR_SREV_KITE_12_OR_LATER(ah)) {
230 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
235 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
238 ar5416AttachPCIE(ah);
241 if (AR_SREV_KITE_12_OR_LATER(ah))
242 AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
243 if (AR_SREV_KITE_11_OR_LATER(ah))
244 AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
246 ecode = ath_hal_v4kEepromAttach(ah);
250 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
251 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
257 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
259 if (!ar5212ChipTest(ah)) {
260 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
270 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
273 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
274 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
279 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
280 AH_PRIVATE(ah)->ah_analog5GhzRev =
285 HALDEBUG(ah, HAL_DEBUG_ANY,
288 AH_PRIVATE(ah)->ah_analog5GhzRev);
293 rfStatus = ar9285RfAttach(ah, &ecode);
295 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
303 if (AR_SREV_9285E_20(ah))
304 ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
307 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
309 if (AR_SREV_9285E_20(ah))
317 if (AR_SREV_9285E_20(ah))
332 if (!ar9285FillCapabilityInfo(ah)) {
342 ar9285_eeprom_print_diversity_settings(ah);
345 if (ar9285_check_div_comb(ah)) {
346 ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
351 AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
353 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
355 HALDEBUG(ah, HAL_DEBUG_ANY,
361 AH_PRIVATE(ah)->ah_currentRD =
362 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
367 AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
376 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
378 ar9285AniSetup(ah); /* Anti Noise Immunity */
381 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
382 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
383 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
386 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
388 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
390 return ah;
392 if (ah != AH_NULL)
393 ah->ah_detach(ah);
400 ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
413 if (AR_SREV_9285E_20(ah)) {
414 val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
418 OS_REG_WRITE(ah, 0x570c, val);
423 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
424 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
438 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
440 val = OS_REG_READ(ah, AR_WA);
459 if (AR_SREV_9285E_20(ah))
462 OS_REG_WRITE(ah, AR_WA, val);
473 if (AR_SREV_9285E_20(ah))
476 OS_REG_WRITE(ah, AR_WA, val);
479 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
484 ar9285DisablePCIE(struct ath_hal *ah)
489 ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
505 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
506 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
507 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
509 if (AR_SREV_KITE_12_OR_LATER(ah)) {
510 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
513 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
523 ar9285FillCapabilityInfo(struct ath_hal *ah)
525 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
527 if (!ar5416FillCapabilityInfo(ah))
539 if (ar9285_check_div_comb(ah))
561 if (AR_SREV_KITE_12_OR_LATER(ah))