Lines Matching refs:ah
21 #include "ah.h"
33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
35 static void ar5416DisablePCIE(struct ath_hal *ah);
36 static void ar5416WriteIni(struct ath_hal *ah,
38 static void ar5416SpurMitigate(struct ath_hal *ah,
42 ar5416AniSetup(struct ath_hal *ah)
63 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
64 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
71 ar5416olcInit(struct ath_hal *ah)
76 ar5416olcTempCompensation(struct ath_hal *ah)
88 struct ath_hal *ah;
92 ah = &ahp->ah_priv.h;
95 ah->ah_magic = AR5416_MAGIC;
96 ah->ah_getRateTable = ar5416GetRateTable;
97 ah->ah_detach = ar5416Detach;
100 ah->ah_reset = ar5416Reset;
101 ah->ah_phyDisable = ar5416PhyDisable;
102 ah->ah_disable = ar5416Disable;
103 ah->ah_configPCIE = ar5416ConfigPCIE;
104 ah->ah_disablePCIE = ar5416DisablePCIE;
105 ah->ah_perCalibration = ar5416PerCalibration;
106 ah->ah_perCalibrationN = ar5416PerCalibrationN;
107 ah->ah_resetCalValid = ar5416ResetCalValid;
108 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
109 ah->ah_setTxPower = ar5416SetTransmitPower;
110 ah->ah_setBoardValues = ar5416SetBoardValues;
113 ah->ah_stopTxDma = ar5416StopTxDma;
114 ah->ah_setupTxDesc = ar5416SetupTxDesc;
115 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
116 ah->ah_fillTxDesc = ar5416FillTxDesc;
117 ah->ah_procTxDesc = ar5416ProcTxDesc;
118 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates;
119 ah->ah_setupTxQueue = ar5416SetupTxQueue;
120 ah->ah_resetTxQueue = ar5416ResetTxQueue;
123 ah->ah_getRxFilter = ar5416GetRxFilter;
124 ah->ah_setRxFilter = ar5416SetRxFilter;
125 ah->ah_stopDmaReceive = ar5416StopDmaReceive;
126 ah->ah_startPcuReceive = ar5416StartPcuReceive;
127 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
128 ah->ah_setupRxDesc = ar5416SetupRxDesc;
129 ah->ah_procRxDesc = ar5416ProcRxDesc;
130 ah->ah_rxMonitor = ar5416RxMonitor;
131 ah->ah_aniPoll = ar5416AniPoll;
132 ah->ah_procMibEvent = ar5416ProcessMibIntr;
135 ah->ah_getCapability = ar5416GetCapability;
136 ah->ah_setCapability = ar5416SetCapability;
137 ah->ah_getDiagState = ar5416GetDiagState;
138 ah->ah_setLedState = ar5416SetLedState;
139 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
140 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
141 ah->ah_gpioGet = ar5416GpioGet;
142 ah->ah_gpioSet = ar5416GpioSet;
143 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
144 ah->ah_getTsf64 = ar5416GetTsf64;
145 ah->ah_setTsf64 = ar5416SetTsf64;
146 ah->ah_resetTsf = ar5416ResetTsf;
147 ah->ah_getRfGain = ar5416GetRfgain;
148 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
149 ah->ah_setDecompMask = ar5416SetDecompMask;
150 ah->ah_setCoverageClass = ar5416SetCoverageClass;
151 ah->ah_setQuiet = ar5416SetQuiet;
152 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts;
153 ah->ah_setChainMasks = ar5416SetChainMasks;
155 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
156 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
159 ah->ah_enableDfs = ar5416EnableDfs;
160 ah->ah_getDfsThresh = ar5416GetDfsThresh;
161 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh;
162 ah->ah_procRadarEvent = ar5416ProcessRadarEvent;
163 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled;
166 ah->ah_spectralConfigure = ar5416ConfigureSpectralScan;
167 ah->ah_spectralGetConfig = ar5416GetSpectralParams;
168 ah->ah_spectralStart = ar5416StartSpectralScan;
169 ah->ah_spectralStop = ar5416StopSpectralScan;
170 ah->ah_spectralIsEnabled = ar5416IsSpectralEnabled;
171 ah->ah_spectralIsActive = ar5416IsSpectralActive;
174 ah->ah_setPowerMode = ar5416SetPowerMode;
177 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
178 ah->ah_beaconInit = ar5416BeaconInit;
179 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
180 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
181 ah->ah_getNextTBTT = ar5416GetNextTBTT;
184 ah->ah_chainTxDesc = ar5416ChainTxDesc;
185 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
186 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
187 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
188 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst;
189 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
190 ah->ah_set11nAggrLast = ar5416Set11nAggrLast;
191 ah->ah_clr11nAggr = ar5416Clr11nAggr;
192 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
193 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
194 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
195 ah->ah_get11nRxClear = ar5416Get11nRxClear;
196 ah->ah_set11nRxClear = ar5416Set11nRxClear;
197 ah->ah_set11nVirtMoreFrag = ar5416Set11nVirtualMoreFrag;
200 ah->ah_isInterruptPending = ar5416IsInterruptPending;
201 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
202 ah->ah_setInterrupts = ar5416SetInterrupts;
205 ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo;
206 ah->ah_btCoexSetConfig = ar5416BTCoexConfig;
207 ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh;
208 ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights;
209 ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh;
210 ah->ah_btCoexSetParameter = ar5416BTCoexSetParameter;
211 ah->ah_btCoexDisable = ar5416BTCoexDisable;
212 ah->ah_btCoexEnable = ar5416BTCoexEnable;
213 AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity;
223 AH5416(ah)->ah_writeIni = ar5416WriteIni;
224 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
227 AH5416(ah)->ah_initPLL = ar5416InitPLL;
230 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware;
233 AH5416(ah)->ah_olcInit = ar5416olcInit;
234 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation;
235 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable;
240 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
241 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
244 AH5416(ah)->ah_ani_function = 0xffffffff;
247 AH5212(ah)->ah_aniControl = ar5416AniControl;
266 if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) {
267 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S);
268 AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1);
270 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_512B >> AR_FTRIG_S);
271 AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1);
276 AH5212(ah)->ah_maxTxTrigLev -= 4;
280 ar5416GetRadioRev(struct ath_hal *ah)
286 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
288 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
289 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
304 struct ath_hal *ah;
325 ah = &ahp->ah_priv.h;
327 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
329 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
334 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
335 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
340 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
341 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
342 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
343 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
349 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
350 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
351 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
352 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
353 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
354 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
355 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
356 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
358 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
359 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n");
365 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
366 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
367 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
370 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
371 ar5416AttachPCIE(ah);
373 ecode = ath_hal_v14EepromAttach(ah);
377 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
378 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
384 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
386 if (!ar5212ChipTest(ah)) {
387 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
397 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
400 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
401 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
408 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
415 AH_PRIVATE(ah)->ah_analog5GhzRev =
421 HALDEBUG(ah, HAL_DEBUG_ANY,
424 AH_PRIVATE(ah)->ah_analog5GhzRev);
433 if (!ar5416FillCapabilityInfo(ah)) {
438 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
440 HALDEBUG(ah, HAL_DEBUG_ANY,
446 AH_PRIVATE(ah)->ah_currentRD =
447 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
448 AH_PRIVATE(ah)->ah_currentRDext =
449 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);
458 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
460 rfStatus = ar2133RfAttach(ah, &ecode);
462 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
467 ar5416AniSetup(ah); /* Anti Noise Immunity */
469 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
470 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
471 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
472 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
473 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
474 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
476 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
478 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
480 return ah;
490 ar5416Detach(struct ath_hal *ah)
492 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
494 HALASSERT(ah != AH_NULL);
495 HALASSERT(ah->ah_magic == AR5416_MAGIC);
498 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
499 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
503 ar5416AniDetach(ah);
504 ar5212RfDetach(ah);
505 ah->ah_disable(ah);
506 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
507 ath_hal_eepromDetach(ah);
508 ath_hal_free(ah);
512 ar5416AttachPCIE(struct ath_hal *ah)
514 if (AH_PRIVATE(ah)->ah_ispcie)
515 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);
517 ath_hal_disablePCIE(ah);
521 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
525 if (! AH_PRIVATE(ah)->ah_ispcie)
529 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
535 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
538 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
541 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
549 ar5416DisablePCIE(struct ath_hal *ah)
553 if (AH_PRIVATE(ah)->ah_ispcie)
557 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah)))
560 OS_REG_WRITE_BUFFER_ENABLE(ah);
565 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
566 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
567 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
568 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
569 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
570 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
571 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
572 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
573 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
576 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
578 OS_REG_WRITE_BUFFER_FLUSH(ah);
579 OS_REG_WRITE_BUFFER_DISABLE(ah);
583 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
608 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
613 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
616 if (AR_SREV_SOWL(ah))
617 ar5416EepromSetAddac(ah, chan);
619 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
621 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
623 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
625 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
629 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
638 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
640 uint16_t freq = ath_hal_gethwchannel(ah, chan);
672 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
686 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
692 OS_REG_WRITE_BUFFER_ENABLE(ah);
694 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
701 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
720 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
748 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
749 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
799 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
800 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
810 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
811 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
821 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
822 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
832 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
833 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
843 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
844 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
854 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
855 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
865 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
866 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
876 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
877 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
879 OS_REG_WRITE_BUFFER_FLUSH(ah);
880 OS_REG_WRITE_BUFFER_DISABLE(ah);
889 ar5416FillCapabilityInfo(struct ath_hal *ah)
891 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
897 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
904 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
925 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
929 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
956 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
961 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
998 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
1000 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
1028 if (AR_SREV_OWL(ah))
1031 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
1032 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
1053 if (! AH_PRIVATE(ah)->ah_ispcie)