Lines Matching defs:ah
25 #include "ah.h"
63 #define ANI_ENA(ah) \
64 (AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)
65 #define ANI_ENA_RSSI(ah) \
66 (AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)
71 enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)
73 struct ath_hal_5212 *ahp = AH5212(ah);
75 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "
79 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
80 OS_REG_WRITE(ah, AR_FILTCCK, 0);
82 OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
83 OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
84 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
85 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
87 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save+clear counters*/
88 ar5212EnableMibCounters(ah); /* enable everything */
92 disableAniMIBCounters(struct ath_hal *ah)
94 struct ath_hal_5212 *ahp = AH5212(ah);
96 HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");
98 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save stats */
99 ar5212DisableMibCounters(ah); /* disable everything */
101 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, 0);
102 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, 0);
106 setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)
109 HALDEBUG(ah, HAL_DEBUG_ANY,
116 HALDEBUG(ah, HAL_DEBUG_ANY,
131 ar5416AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,
134 struct ath_hal_5212 *ahp = AH5212(ah);
138 setPhyErrBase(ah, &ahp->ah_aniParams24);
142 setPhyErrBase(ah, &ahp->ah_aniParams5);
147 enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);
163 ar5416AniDetach(struct ath_hal *ah)
165 HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");
166 disableAniMIBCounters(ah);
173 ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
176 struct ath_hal_5212 *ahp = AH5212(ah);
187 OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);
197 ar5416AniDetach(ah);
206 enableAniMIBCounters(ah,
217 if (((1 << cmd) & AH5416(ah)->ah_ani_function) == 0) {
218 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: command %d disabled\n",
220 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: cmd %d; mask %x\n", __func__, cmd, AH5416(ah)->ah_ani_function);
229 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_NOISE_IMMUNITY_LEVEL: set level = %d\n", __func__, level);
231 HALDEBUG(ah, HAL_DEBUG_ANI,
237 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
239 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
241 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
243 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
262 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: %s\n", __func__, on ? "enabled" : "disabled");
263 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
265 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
267 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
269 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
271 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
273 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
276 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
278 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
280 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
282 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
286 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
289 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
303 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_CCK_WEAK_SIGNAL_THR: %s\n", __func__, high ? "high" : "low");
304 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
316 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_FIRSTEP_LEVEL: level = %d\n", __func__, level);
318 HALDEBUG(ah, HAL_DEBUG_ANI,
323 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
335 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_SPUR_IMMUNITY_LEVEL: level = %d\n", __func__, level);
337 HALDEBUG(ah, HAL_DEBUG_ANI,
342 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
359 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: invalid cmd %u\n",
367 ar5416AniOfdmErrTrigger(struct ath_hal *ah)
369 struct ath_hal_5212 *ahp = AH5212(ah);
370 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
376 if (!ANI_ENA(ah))
383 if (ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
389 if (ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
399 if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {
401 if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
406 if (ANI_ENA_RSSI(ah)) {
414 ar5416AniControl(ah,
417 ar5416AniControl(ah,
426 if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
436 ar5416AniControl(ah,
440 if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
451 ar5416AniControl(ah,
455 if (ar5416AniControl(ah,
464 ar5416AniCckErrTrigger(struct ath_hal *ah)
466 struct ath_hal_5212 *ahp = AH5212(ah);
467 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
473 if (!ANI_ENA(ah))
479 if ((AH5416(ah)->ah_ani_function & (1 << HAL_ANI_NOISE_IMMUNITY_LEVEL) &&
481 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
486 if (ANI_ENA_RSSI(ah)) {
494 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
503 ar5416AniControl(ah,
511 ar5416AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
513 struct ath_hal_5212 *ahp = AH5212(ah);
521 HALDEBUG(ah, HAL_DEBUG_ANI,
524 OS_REG_WRITE(ah, AR_PHY_ERR_1, params->ofdmPhyErrBase);
525 OS_REG_WRITE(ah, AR_PHY_ERR_2, params->cckPhyErrBase);
526 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
527 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
530 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
543 ar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,
546 struct ath_hal_5212 *ahp = AH5212(ah);
547 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
563 ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",
567 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",
571 OS_MARK(ah, AH_MARK_ANI_RESET, opmode);
576 rxfilter = ah->ah_getRxFilter(ah);
577 ah->ah_setRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);
584 if (! ANI_ENA(ah)) {
585 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ANI disabled\n",
595 AH5416(ah)->ah_ani_function =
598 AH5416(ah)->ah_ani_function = 0;
615 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
617 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
619 ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
621 ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
623 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
626 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
627 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
628 ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
630 ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
631 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
638 enableAniMIBCounters(ah, aniState->params);
639 ar5416AniRestart(ah, aniState);
643 ah->ah_setRxFilter(ah, rxfilter);
652 ar5416ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
654 struct ath_hal_5212 *ahp = AH5212(ah);
657 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "
659 __func__, OS_REG_READ(ah, AR_MIBC),
660 OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
661 OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
673 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
674 phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
676 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
677 OS_REG_WRITE(ah, AR_FILTCCK, 0);
678 if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)
679 OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
682 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
714 ar5416AniOfdmErrTrigger(ah);
716 ar5416AniCckErrTrigger(ah);
718 ar5416AniRestart(ah, aniState);
723 ar5416AniLowerImmunity(struct ath_hal *ah)
725 struct ath_hal_5212 *ahp = AH5212(ah);
729 HALASSERT(ANI_ENA(ah));
739 if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {
741 if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
746 if (ANI_ENA_RSSI(ah)) {
760 if (ar5416AniControl(ah,
766 if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
775 if (ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
783 if (ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
792 if (ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
814 ar5416AniGetListenTime(struct ath_hal *ah)
816 struct ath_hal_5212 *ahp = AH5212(ah);
825 if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {
826 ath_hal_printf(ah, "%s: ah_curchan = NULL?\n", __func__);
835 good = ar5416GetMibCycleCounts(ah, &hs);
836 ath_hal_survey_add_sample(ah, &hs);
838 if (ANI_ENA(ah))
849 } else if (ANI_ENA(ah)) {
855 AH5416(ah)->ah_cycleCount - aniState->cycleCount;
857 AH5416(ah)->ah_rxBusy - aniState->rxFrameCount;
859 AH5416(ah)->ah_txBusy - aniState->txFrameCount;
866 if (ANI_ENA(ah)) {
867 aniState->cycleCount = AH5416(ah)->ah_cycleCount;
868 aniState->rxFrameCount = AH5416(ah)->ah_rxBusy;
869 aniState->txFrameCount = AH5416(ah)->ah_txBusy;
879 updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
881 struct ath_hal_5212 *ahp = AH5212(ah);
887 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
890 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
891 phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
896 HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",
906 HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",
916 ar5416RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,
919 struct ath_hal_5212 *ahp = AH5212(ah);
928 ar5416AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)
930 struct ath_hal_5212 *ahp = AH5212(ah);
936 listenTime = ar5416AniGetListenTime(ah);
942 if (!ANI_ENA(ah))
948 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: invalid listenTime\n",
950 ar5416AniRestart(ah, aniState);
955 OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);
963 updateMIBStats(ah, aniState);
968 ar5416AniLowerImmunity(ah);
969 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower immunity\n",
971 ar5416AniRestart(ah, aniState);
973 updateMIBStats(ah, aniState);
977 HALDEBUG(ah, HAL_DEBUG_ANI,
980 ar5416AniOfdmErrTrigger(ah);
981 ar5416AniRestart(ah, aniState);
984 HALDEBUG(ah, HAL_DEBUG_ANI,
987 ar5416AniCckErrTrigger(ah);
988 ar5416AniRestart(ah, aniState);