Lines Matching defs:ah
23 #include "ah.h"
40 extern HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,
56 write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
71 OS_REG_WRITE(ah, reg, V(i, 1));
89 ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
97 struct ath_hal_5212 *ahp = AH5212(ah);
110 HALASSERT(ah->ah_magic == AR5212_MAGIC);
111 ee = AH_PRIVATE(ah)->ah_eeprom;
113 OS_MARK(ah, AH_MARK_RESET, bChannelChange);
117 ichan = ath_hal_checkchannel(ah, chan);
119 HALDEBUG(ah, HAL_DEBUG_ANY,
131 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
160 saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
165 if ((IS_2413(ah) || IS_5413(ah))) {
174 AH_PRIVATE(ah)->ah_curchan != AH_NULL &&
175 (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&
177 (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {
178 if (ar5212ChannelChange(ah, chan))
187 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
192 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
196 if (!IS_5315(ah))
197 saveLedState = OS_REG_READ(ah, AR5312_PCICFG) &
201 ar5312RestoreClock(ah, opmode); /* move to refclk operation */
207 (void) ar5212GetRfgain(ah);
209 if (!ar5312ChipReset(ah, chan)) {
210 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
224 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
227 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
229 regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
230 regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
232 ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
234 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
237 ar5212SetIFSTiming(ah, chan);
240 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
242 OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
256 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
260 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
264 OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,
266 OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
270 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
273 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
275 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);
277 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
280 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
282 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
286 if (IS_5312_2_X(ah)) {
288 OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA,
295 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);
299 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);
302 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
306 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
309 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
313 if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {
314 HALDEBUG(ah, HAL_DEBUG_ANY,
320 if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) {
321 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
328 if (IS_5413(ah) ||
329 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)
330 ar5212SetSpurMitigation(ah, chan);
331 ar5212SetDeltaSlope(ah, chan);
335 if (!ar5212SetBoardValues(ah, chan)) {
336 HALDEBUG(ah, HAL_DEBUG_ANY,
343 OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);
345 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
347 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
348 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
353 ar5212SetOperatingMode(ah, opmode);
356 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
357 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
360 if (!IS_5315(ah))
361 OS_REG_WRITE(ah, AR5312_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);
364 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
367 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
368 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
371 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
373 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
375 if (!ar5212SetChannel(ah, chan))
378 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
380 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
382 ar5212SetRateDurationTable(ah, chan);
385 if (IS_RAD5112_ANY(ah) &&
391 OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
413 if (IS_5312_2_X(ah)) {
414 (void) OS_REG_READ(ah, AR_PHY_SLEEP_SCAL);
422 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
430 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
451 testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);
453 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);
456 (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200);
457 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);
460 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
461 OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
467 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
470 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
477 ar5212SetCompRegs(ah);
481 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
484 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
485 ar5212ResetTxQueue(ah, i);
499 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
501 OS_REG_WRITE(ah, AR_IMR_S2,
502 OS_REG_READ(ah, AR_IMR_S2)
505 if (AH_PRIVATE(ah)->ah_rfkillEnabled)
506 ar5212EnableRfKill(ah);
508 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
509 HALDEBUG(ah, HAL_DEBUG_ANY,
518 ar5312SetupClock(ah, opmode);
526 OS_REG_WRITE(ah, AR_BEACON,
527 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
532 if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||
533 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
534 AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {
535 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */
536 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */
540 OS_REG_WRITE(ah, AR_NOACK,
547 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
549 ar5212SetSlotTime(ah, ahp->ah_slottime);
551 ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
553 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
555 ar5212SetSifsTime(ah, ahp->ah_sifstime);
556 if (AH_PRIVATE(ah)->ah_diagreg != 0)
557 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
559 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
564 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
566 OS_MARK(ah, AH_MARK_RESET_DONE, 0);
570 OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
585 ar5312PhyDisable(struct ath_hal *ah)
587 return ar5312SetResetReg(ah, AR_RC_BB);
594 ar5312Disable(struct ath_hal *ah)
596 if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
602 return ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB);
613 ar5312ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
616 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
621 if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) {
622 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
628 if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
629 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed\n",
635 if (!ar5312SetResetReg(ah, 0)) {
636 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
654 if (IS_RAD5112_ANY(ah)) {
656 if (!IS_5315(ah)) {
701 curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
710 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
711 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
713 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);
719 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);
723 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
724 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
734 ar5312SetResetReg(struct ath_hal *ah, uint32_t resetMask)
739 if ((rt = ar5312MacReset(ah, mask)) == AH_FALSE) {
753 OS_REG_WRITE(ah, AR_CFG, mask);
755 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
767 ar5312MacReset(struct ath_hal *ah, unsigned int RCMask)
769 int wlanNum = AR5312_UNIT(ah);
776 if (IS_5315(ah)) {
794 reg = OS_REG_READ(ah,
795 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5315_RESET));
808 OS_REG_WRITE(ah,
809 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
812 OS_REG_READ(ah,
813 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5315_RESET));
819 OS_REG_READ(ah,
820 (AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
821 OS_REG_WRITE(ah,
822 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
825 OS_REG_READ(ah,
826 (AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
851 reg = OS_REG_READ(ah,
852 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5312_RESET));
865 OS_REG_WRITE(ah,
866 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
869 OS_REG_READ(ah,
870 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5312_RESET));
876 OS_REG_READ(ah,
877 (AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));
878 OS_REG_WRITE(ah,
879 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
882 OS_REG_READ(ah,
883 (AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));