ath_hal/ar5312/ar5312_misc.c

23 #include "ah.h"
38 ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
41 	uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh));
42     if(IS_2316(ah)) return; /* not yet */
46 	OS_REG_WRITE(ah, resOffset+AR5312_PCICFG,
47 		(OS_REG_READ(ah, AR5312_PCICFG) &~
57 ar5312DetectCardPresent(struct ath_hal *ah)
68     if(IS_5315(ah))
70 		v = (OS_REG_READ(ah,
71                          (AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV))
75 		return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
76 				AH_PRIVATE(ah)->ah_macRev == macRev);
81 		v = (OS_REG_READ(ah,
82                          (AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV))
86 		return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
87 				AH_PRIVATE(ah)->ah_macRev == macRev);
98 ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
100 	if (ar5212Use32KHzclock(ah, opmode)) {
106 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
107 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x0d);
108 		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0c);
109 		OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x03);
110 		OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0x05);
111 		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
112 		    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
114 		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
115 		OS_REG_WRITE(ah, AR_TSF_PARM, 61);	/* 32 KHz TSF incr */
118 		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
119 		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
120 		    IS_RAD5112_ANY(ah) ? 39 : 31);
122 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
123 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
125 		if (IS_5312_2_X(ah)) {
127 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x04);
129 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
130 			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
131 			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
132 			OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
133 			    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
142 ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
144 	if (ar5212Use32KHzclock(ah, opmode)) {
146 		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
147 		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
148 		    IS_RAD5112_ANY(ah) ? 39 : 31);
153 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
154 		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
155 		if (IS_5312_2_X(ah)) {
157 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x04);
159 			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
160 			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
161 			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
162 			OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
163 			    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);