Lines Matching defs:ah
21 #include "ah.h"
59 #define ANI_ENA(ah) \
60 (AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)
61 #define ANI_ENA_RSSI(ah) \
62 (AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)
67 enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)
69 struct ath_hal_5212 *ahp = AH5212(ah);
71 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "
75 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
76 OS_REG_WRITE(ah, AR_FILTCCK, 0);
78 OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
79 OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
80 OS_REG_WRITE(ah, AR_PHYCNTMASK1, AR_PHY_ERR_OFDM_TIMING);
81 OS_REG_WRITE(ah, AR_PHYCNTMASK2, AR_PHY_ERR_CCK_TIMING);
83 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save+clear counters*/
84 ar5212EnableMibCounters(ah); /* enable everything */
88 disableAniMIBCounters(struct ath_hal *ah)
90 struct ath_hal_5212 *ahp = AH5212(ah);
92 HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");
94 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save stats */
95 ar5212DisableMibCounters(ah); /* disable everything */
97 OS_REG_WRITE(ah, AR_PHYCNTMASK1, 0);
98 OS_REG_WRITE(ah, AR_PHYCNTMASK2, 0);
105 ar5212AniGetCurrentState(struct ath_hal *ah)
107 return AH5212(ah)->ah_curani;
114 ar5212AniGetCurrentStats(struct ath_hal *ah)
116 struct ath_hal_5212 *ahp = AH5212(ah);
120 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
125 setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)
128 HALDEBUG(ah, HAL_DEBUG_ANY,
135 HALDEBUG(ah, HAL_DEBUG_ANY,
150 ar5212AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,
153 struct ath_hal_5212 *ahp = AH5212(ah);
156 AH_PRIVATE(ah)->ah_caps.halHwPhyCounterSupport;
160 setPhyErrBase(ah, &ahp->ah_aniParams24);
164 setPhyErrBase(ah, &ahp->ah_aniParams5);
170 enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);
181 ar5212AniSetParams(struct ath_hal *ah, const struct ar5212AniParams *params24,
184 struct ath_hal_5212 *ahp = AH5212(ah);
187 ar5212AniControl(ah, HAL_ANI_MODE, AH_FALSE);
190 setPhyErrBase(ah, &ahp->ah_aniParams24);
192 setPhyErrBase(ah, &ahp->ah_aniParams5);
195 ar5212AniReset(ah, AH_PRIVATE(ah)->ah_curchan,
196 AH_PRIVATE(ah)->ah_opmode, AH_FALSE);
198 ar5212AniControl(ah, HAL_ANI_MODE, ena);
207 ar5212AniDetach(struct ath_hal *ah)
209 struct ath_hal_5212 *ahp = AH5212(ah);
211 HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");
213 disableAniMIBCounters(ah);
220 ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
223 struct ath_hal_5212 *ahp = AH5212(ah);
234 OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);
241 HALDEBUG(ah, HAL_DEBUG_ANY,
247 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
249 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
251 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
253 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
272 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
274 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
276 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
278 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
280 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
282 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
286 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
290 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
301 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
314 HALDEBUG(ah, HAL_DEBUG_ANY,
319 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
332 HALDEBUG(ah, HAL_DEBUG_ANY,
337 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
352 ar5212AniDetach(ah);
353 ah->ah_setRxFilter(ah,
354 ah->ah_getRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
360 ar5212SetRxFilter(ah,
361 ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
363 enableAniMIBCounters(ah,
368 ah->ah_setRxFilter(ah,
369 ah->ah_getRxFilter(ah) | HAL_RX_FILTER_PHYERR);
381 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid cmd %u\n",
389 ar5212AniOfdmErrTrigger(struct ath_hal *ah)
391 struct ath_hal_5212 *ahp = AH5212(ah);
392 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
398 if (!ANI_ENA(ah))
405 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
407 ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
413 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise SI to %u\n", __func__,
415 ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
420 if (ANI_ENA_RSSI(ah)) {
428 HALDEBUG(ah, HAL_DEBUG_ANI,
430 ar5212AniControl(ah,
433 ar5212AniControl(ah,
442 HALDEBUG(ah, HAL_DEBUG_ANI,
445 ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
455 HALDEBUG(ah, HAL_DEBUG_ANI,
457 ar5212AniControl(ah,
462 HALDEBUG(ah, HAL_DEBUG_ANI,
465 ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
477 HALDEBUG(ah, HAL_DEBUG_ANI,
480 ar5212AniControl(ah,
485 HALDEBUG(ah, HAL_DEBUG_ANI,
489 ar5212AniControl(ah,
499 ar5212AniCckErrTrigger(struct ath_hal *ah)
501 struct ath_hal_5212 *ahp = AH5212(ah);
502 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
508 if (!ANI_ENA(ah))
515 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
517 ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
522 if (ANI_ENA_RSSI(ah)) {
530 HALDEBUG(ah, HAL_DEBUG_ANI,
533 ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
545 HALDEBUG(ah, HAL_DEBUG_ANI,
549 ar5212AniControl(ah,
558 ar5212AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
560 struct ath_hal_5212 *ahp = AH5212(ah);
569 OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
570 OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
571 OS_REG_WRITE(ah, AR_PHYCNTMASK1, AR_PHY_ERR_OFDM_TIMING);
572 OS_REG_WRITE(ah, AR_PHYCNTMASK2, AR_PHY_ERR_CCK_TIMING);
575 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
586 ar5212AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,
589 struct ath_hal_5212 *ahp = AH5212(ah);
590 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
606 ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",
610 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",
614 OS_MARK(ah, AH_MARK_ANI_RESET, opmode);
619 rxfilter = ah->ah_getRxFilter(ah);
620 ah->ah_setRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);
627 if (! ANI_ENA(ah)) {
628 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ANI disabled\n",
647 ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
649 ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
651 ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
653 ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
655 ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
658 ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
659 ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
660 ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
662 ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
663 ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
669 enableAniMIBCounters(ah, ahp->ah_curani->params);
670 ar5212AniRestart(ah, aniState);
674 ah->ah_setRxFilter(ah, rxfilter);
683 ar5212ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
685 struct ath_hal_5212 *ahp = AH5212(ah);
688 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "
690 __func__, OS_REG_READ(ah, AR_MIBC),
691 OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
692 OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
704 phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);
705 phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);
707 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
708 OS_REG_WRITE(ah, AR_FILTCCK, 0);
711 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
743 ar5212AniOfdmErrTrigger(ah);
745 ar5212AniCckErrTrigger(ah);
747 ar5212AniRestart(ah, aniState);
752 ar5212AniPhyErrReport(struct ath_hal *ah, const struct ath_rx_status *rs)
754 struct ath_hal_5212 *ahp = AH5212(ah);
766 ar5212AniOfdmErrTrigger(ah);
767 ar5212AniRestart(ah, aniState);
773 ar5212AniCckErrTrigger(ah);
774 ar5212AniRestart(ah, aniState);
780 ar5212AniLowerImmunity(struct ath_hal *ah)
782 struct ath_hal_5212 *ahp = AH5212(ah);
786 HALASSERT(ANI_ENA(ah));
790 if (ANI_ENA_RSSI(ah)) {
804 HALDEBUG(ah, HAL_DEBUG_ANI,
806 ar5212AniControl(ah,
812 HALDEBUG(ah, HAL_DEBUG_ANI,
815 ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
824 HALDEBUG(ah, HAL_DEBUG_ANI,
827 ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
835 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower SI %u\n",
837 ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
846 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower NI %u\n",
848 ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
865 ar5212AniGetListenTime(struct ath_hal *ah)
867 struct ath_hal_5212 *ahp = AH5212(ah);
876 if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {
877 ath_hal_printf(ah, "%s: ah_curchan = NULL?\n", __func__);
886 good = ar5212GetMibCycleCounts(ah, &hs);
887 ath_hal_survey_add_sample(ah, &hs);
889 if (ANI_ENA(ah))
900 } else if (ANI_ENA(ah)) {
906 AH5212(ah)->ah_cycleCount - aniState->cycleCount;
908 AH5212(ah)->ah_rxBusy - aniState->rxFrameCount;
910 AH5212(ah)->ah_txBusy - aniState->txFrameCount;
917 if (ANI_ENA(ah)) {
918 aniState->cycleCount = AH5212(ah)->ah_cycleCount;
919 aniState->rxFrameCount = AH5212(ah)->ah_rxBusy;
920 aniState->txFrameCount = AH5212(ah)->ah_txBusy;
930 updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
932 struct ath_hal_5212 *ahp = AH5212(ah);
940 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
943 phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);
944 phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);
949 HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",
959 HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",
969 ar5212RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,
972 struct ath_hal_5212 *ahp = AH5212(ah);
981 ar5212AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)
983 struct ath_hal_5212 *ahp = AH5212(ah);
989 listenTime = ar5212AniGetListenTime(ah);
994 if (!ANI_ENA(ah))
1000 ar5212AniRestart(ah, aniState);
1005 OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);
1014 updateMIBStats(ah, aniState);
1019 ar5212AniLowerImmunity(ah);
1020 ar5212AniRestart(ah, aniState);
1023 updateMIBStats(ah, aniState);
1027 HALDEBUG(ah, HAL_DEBUG_ANI,
1030 ar5212AniOfdmErrTrigger(ah);
1031 ar5212AniRestart(ah, aniState);
1034 HALDEBUG(ah, HAL_DEBUG_ANI,
1037 ar5212AniCckErrTrigger(ah);
1038 ar5212AniRestart(ah, aniState);