ath_hal/ar5211/ar5211_misc.c

21 #include "ah.h"
34 ar5211GetMacAddress(struct ath_hal *ah, uint8_t *mac)
36 	struct ath_hal_5211 *ahp = AH5211(ah);
42 ar5211SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
44 	struct ath_hal_5211 *ahp = AH5211(ah);
51 ar5211GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
59 ar5211SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
68 ar5211EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
70 	OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);
71 	OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);
73 	if (!ath_hal_wait(ah, AR_EEPROM_STS,
76 		HALDEBUG(ah, HAL_DEBUG_ANY,
80 	*data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
89 ar5211EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
99 ar5211SetRegulatoryDomain(struct ath_hal *ah,
104 	if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
113 	if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
118 	if (ar5211EepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
119 		HALDEBUG(ah, HAL_DEBUG_ANY,
122 		AH_PRIVATE(ah)->ah_currentRD = regDomain;
141 ar5211GetWirelessModes(struct ath_hal *ah)
145 	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
147 		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
150 	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
157 ar5211GetTurboDisable(struct ath_hal *ah)
159 	return (AH5211(ah)->ah_turboDisable != 0);
168 ar5211EnableRfKill(struct ath_hal *ah)
170 	uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
178 	ar5211GpioCfgInput(ah, select);
179 	OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);
188 	ar5211GpioSetIntr(ah, select, (ar5211GpioGet(ah, select) != polarity));
195 ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
201 	reg =  OS_REG_READ(ah, AR_GPIOCR);
205 	OS_REG_WRITE(ah, AR_GPIOCR, reg);
213 ar5211GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
219 	reg =  OS_REG_READ(ah, AR_GPIOCR);
223 	OS_REG_WRITE(ah, AR_GPIOCR, reg);
231 ar5211GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
237 	reg =  OS_REG_READ(ah, AR_GPIODO);
241 	OS_REG_WRITE(ah, AR_GPIODO, reg);
249 ar5211GpioGet(struct ath_hal *ah, uint32_t gpio)
252 		uint32_t val = OS_REG_READ(ah, AR_GPIODI);
264 ar5211GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
266 	uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
277 	OS_REG_WRITE(ah, AR_GPIOCR, val);
280 	ar5211SetInterrupts(ah, AH5211(ah)->ah_maskReg | HAL_INT_GPIO);
287 ar5211SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
299 	OS_REG_WRITE(ah, AR_PCICFG,
300 		(OS_REG_READ(ah, AR_PCICFG) &~
313 ar5211WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
315 	struct ath_hal_5211 *ahp = AH5211(ah);
319 	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
320 	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
328 ar5211GetTsf64(struct ath_hal *ah)
333 	low1 = OS_REG_READ(ah, AR_TSF_L32);
334 	u32 = OS_REG_READ(ah, AR_TSF_U32);
335 	low2 = OS_REG_READ(ah, AR_TSF_L32);
356 ar5211GetTsf32(struct ath_hal *ah)
358 	return OS_REG_READ(ah, AR_TSF_L32);
365 ar5211ResetTsf(struct ath_hal *ah)
367 	uint32_t val = OS_REG_READ(ah, AR_BEACON);
369 	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
377 ar5211GetRandomSeed(struct ath_hal *ah)
381 	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
384 	return (OS_REG_READ(ah, AR_TSF_U32) ^
385 		OS_REG_READ(ah, AR_TSF_L32) ^ nf);
392 ar5211DetectCardPresent(struct ath_hal *ah)
402 	v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;
405 	return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
406 		AH_PRIVATE(ah)->ah_macRev == macRev);
413 ar5211UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
415 	stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
416 	stats->rts_bad	  += OS_REG_READ(ah, AR_RTS_FAIL);
417 	stats->fcs_bad	  += OS_REG_READ(ah, AR_FCS_FAIL);
418 	stats->rts_good	  += OS_REG_READ(ah, AR_RTS_OK);
419 	stats->beacons	  += OS_REG_READ(ah, AR_BEACON_CNT);
423 ar5211SetSifsTime(struct ath_hal *ah, u_int us)
425 	struct ath_hal_5211 *ahp = AH5211(ah);
427 	if (us > ath_hal_mac_usec(ah, 0xffff)) {
428 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
434 		OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));
441 ar5211GetSifsTime(struct ath_hal *ah)
443 	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
444 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
448 ar5211SetSlotTime(struct ath_hal *ah, u_int us)
450 	struct ath_hal_5211 *ahp = AH5211(ah);
452 	if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
453 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
459 		OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
466 ar5211GetSlotTime(struct ath_hal *ah)
468 	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
469 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
473 ar5211SetAckTimeout(struct ath_hal *ah, u_int us)
475 	struct ath_hal_5211 *ahp = AH5211(ah);
477 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
478 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
484 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
485 			AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
492 ar5211GetAckTimeout(struct ath_hal *ah)
494 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
495 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
499 ar5211GetAckCTSRate(struct ath_hal *ah)
501 	return ((AH5211(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
505 ar5211SetAckCTSRate(struct ath_hal *ah, u_int high)
507 	struct ath_hal_5211 *ahp = AH5211(ah);
510 		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
513 		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
520 ar5211SetCTSTimeout(struct ath_hal *ah, u_int us)
522 	struct ath_hal_5211 *ahp = AH5211(ah);
524 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
525 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
531 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
532 			AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
539 ar5211GetCTSTimeout(struct ath_hal *ah)
541 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
542 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
546 ar5211SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
553 ar5211SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
561 ar5211AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
567 ar5211AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)
572 ar5211RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,
578 ar5211MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
586 ar5211GetCurRssi(struct ath_hal *ah)
588 	return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
592 ar5211GetDefAntenna(struct ath_hal *ah)
594 	return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
598 ar5211SetDefAntenna(struct ath_hal *ah, u_int antenna)
600 	OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
604 ar5211GetAntennaSwitch(struct ath_hal *ah)
606 	return AH5211(ah)->ah_diversityControl;
610 ar5211SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
612 	const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
615 		AH5211(ah)->ah_diversityControl = settings;
618 	return ar5211SetAntennaSwitchInternal(ah, settings, chan);
622 ar5211GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
637 		return ath_hal_getcapability(ah, type, capability, result);
642 ar5211SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
653 		AH_PRIVATE(ah)->ah_diagreg = setting;
655 		AH_PRIVATE(ah)->ah_diagreg = setting & 0x6;	/* ACK+CTS */
657 		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
660 		return ath_hal_setcapability(ah, type, capability,
666 ar5211GetDiagState(struct ath_hal *ah, int request,
670 	struct ath_hal_5211 *ahp = AH5211(ah);
673 	if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
677 		return ath_hal_eepromDiag(ah, request,
697 ar5211Get11nExtBusy(struct ath_hal *ah)
707 ar5211GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
714 ar5211SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,
720 ar5211EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
725 ar5211GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)