Lines Matching refs:val
191 ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
199 reg |= (val&1) << gpio;
212 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
213 val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
214 return val;
226 uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
229 val &= ~(AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA |
232 val |= AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_ENA;
234 val |= AR_GPIOCR_INT_SELH;
237 OS_REG_WRITE(ah, AR_GPIOCR, val);
249 uint32_t val;
251 val = OS_REG_READ(ah, AR_PCICFG);
254 val &= ~(AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
258 val &= ~AR_PCICFG_LED_PEND;
259 val |= AR_PCICFG_LED_ACT;
262 val |= AR_PCICFG_LED_PEND;
263 val &= ~AR_PCICFG_LED_ACT;
266 OS_REG_WRITE(ah, AR_PCICFG, val);
275 uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
276 return (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1);
282 uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
284 if (antenna != (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1)) {
288 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);
371 uint32_t val = OS_REG_READ(ah, AR_BEACON);
373 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
697 ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val)
701 val |= AR_DIAG_SW_DIS_CRYPTO;
702 OS_REG_WRITE(ah, AR_DIAG_SW, val);