dev/agp/agp_intel.c

40 #include <dev/agp/agppriv.h>
41 #include <dev/agp/agpreg.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
60 agp_intel_match(device_t dev)
62 	if (pci_get_class(dev) != PCIC_BRIDGE
63 	    || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
66 	if (agp_find_caps(dev) == 0)
69 	switch (pci_get_devid(dev)) {
114 agp_intel_probe(device_t dev)
118 	if (resource_disabled("agp", device_get_unit(dev)))
120 	desc = agp_intel_match(dev);
122 		device_set_desc(dev, desc);
130 agp_intel_commit_gatt(device_t dev)
136 	sc = device_get_softc(dev);
137 	type = pci_get_devid(dev);
140 	pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4);
145 		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
152 		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
155 		value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
156 		pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
163 		pci_write_config(dev, AGP_INTEL_I820_RDCR,
164 				 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
173 		pci_write_config(dev, AGP_INTEL_I845_AGPM,
174 				 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
182 		pci_write_config(dev, AGP_INTEL_MCHCFG,
183 				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
187 		pci_write_config(dev, AGP_INTEL_NBXCFG,
188 				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
195 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
208 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
211 		pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
216 agp_intel_attach(device_t dev)
223 	sc = device_get_softc(dev);
225 	error = agp_generic_attach(dev);
230 	value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
231 	pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
232 	sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
234 	pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
235 	sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev);
238 		gatt = agp_alloc_gatt(dev);
246 		if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
247 			agp_generic_detach(dev);
253 	agp_intel_commit_gatt(dev);
259 agp_intel_detach(device_t dev)
264 	sc = device_get_softc(dev);
266 	agp_free_cdev(dev);
269 	switch (pci_get_devid(dev)) {
272 		reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
274 		pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
282 		reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
284 		pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
291 		reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
293 		pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
296 		reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
298 		pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
300 	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
301 	AGP_SET_APERTURE(dev, sc->initial_aperture);
303 	agp_free_res(dev);
309 agp_intel_resume(device_t dev)
312 	sc = device_get_softc(dev);
314 	AGP_SET_APERTURE(dev, sc->current_aperture);
315 	agp_intel_commit_gatt(dev);
316 	return (bus_generic_resume(dev));
320 agp_intel_get_aperture(device_t dev)
325 	sc = device_get_softc(dev);
327 	apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
340 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
345 	sc = device_get_softc(dev);
360 	pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
366 agp_intel_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
370 	sc = device_get_softc(dev);
380 agp_intel_unbind_page(device_t dev, vm_offset_t offset)
384 	sc = device_get_softc(dev);
394 agp_intel_flush_tlb(device_t dev)
398 	val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
399 	pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
400 	pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);