Lines Matching refs:sc
97 struct hpet_softc *sc;
134 static void hpet_test(struct hpet_softc *sc);
144 struct hpet_softc *sc;
146 sc = tc->tc_priv;
147 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
153 struct hpet_softc *sc;
155 sc = tc->tc_priv;
158 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev);
160 return (sc->mmap_allow != 0);
168 struct hpet_softc *sc;
170 sc = tc->tc_priv;
173 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev);
175 return (sc->mmap_allow != 0);
180 hpet_enable(struct hpet_softc *sc)
184 val = bus_read_4(sc->mem_res, HPET_CONFIG);
185 if (sc->legacy_route)
190 bus_write_4(sc->mem_res, HPET_CONFIG, val);
194 hpet_disable(struct hpet_softc *sc)
198 val = bus_read_4(sc->mem_res, HPET_CONFIG);
200 bus_write_4(sc->mem_res, HPET_CONFIG, val);
208 struct hpet_softc *sc = mt->sc;
211 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
214 t->div = (sc->freq * period) >> 32;
220 fdiv = (sc->freq * first) >> 32;
224 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
226 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
231 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
233 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
235 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
239 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
241 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
244 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
257 struct hpet_softc *sc = mt->sc;
259 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
262 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
271 struct hpet_softc *sc = t->sc;
291 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
292 sc->freq / 8;
293 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
301 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
304 bus_write_4(sc->mem_res,
308 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
317 struct hpet_softc *sc = (struct hpet_softc *)arg;
321 val = bus_read_4(sc->mem_res, HPET_ISR);
323 bus_write_4(sc->mem_res, HPET_ISR, val);
324 val &= sc->useirq;
325 for (i = 0; i < sc->num_timers; i++) {
328 hpet_intr_single(&sc->t[i]);
338 struct hpet_softc *sc;
340 sc = device_get_softc(dev);
341 return (sc->acpi_uid);
384 struct hpet_softc *sc;
386 sc = cdev->si_drv1;
387 if (!sc->mmap_allow)
397 struct hpet_softc *sc;
399 sc = cdev->si_drv1;
400 if (offset > rman_get_size(sc->mem_res))
402 if (!sc->mmap_allow_write && (nprot & PROT_WRITE))
404 *paddr = rman_get_start(sc->mem_res) + offset;
469 struct hpet_softc *sc;
480 sc = device_get_softc(dev);
481 sc->dev = dev;
482 sc->handle = acpi_get_handle(dev);
484 sc->mem_rid = 0;
485 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
487 if (sc->mem_res == NULL)
491 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
493 rman_get_size(sc->mem_res));
494 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
499 hpet_enable(sc);
502 val = bus_read_4(sc->mem_res, HPET_PERIOD);
505 hpet_disable(sc);
506 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
510 sc->freq = (1000000000000000LL + val / 2) / val;
511 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
512 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
513 rev = sc->caps & HPET_CAP_REV_ID;
514 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
523 sc->num_timers = num_timers;
527 vendor, rev, sc->freq,
528 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
530 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
533 t = &sc->t[i];
534 t->sc = sc;
542 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
543 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
554 hpet_test(sc);
559 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
561 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
564 hpet_disable(sc);
565 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
570 sc->tc.tc_get_timecount = hpet_get_timecount,
571 sc->tc.tc_counter_mask = ~0u,
572 sc->tc.tc_name = "HPET",
573 sc->tc.tc_quality = 950,
574 sc->tc.tc_frequency = sc->freq;
575 sc->tc.tc_priv = sc;
576 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands;
578 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32;
580 tc_init(&sc->tc);
588 sc->legacy_route = 0;
590 "legacy_route", &sc->legacy_route);
591 if ((sc->caps & HPET_CAP_LEG_RT) == 0)
592 sc->legacy_route = 0;
593 if (sc->legacy_route) {
594 sc->t[0].vectors = 0;
595 sc->t[1].vectors = 0;
600 sc->allowed_irqs = 0xffff0000;
609 sc->allowed_irqs = 0x00000000;
615 sc->allowed_irqs = 0x00000000;
622 sc->allowed_irqs = 0x00000000;
629 sc->allowed_irqs = 0x00000000;
632 "allowed_irqs", &sc->allowed_irqs);
635 sc->per_cpu = 1;
637 "per_cpu", &sc->per_cpu);
640 sc->useirq = 0;
642 cvectors = sc->allowed_irqs & 0xffff0000;
643 dvectors = sc->allowed_irqs & 0x0000ffff;
644 if (sc->legacy_route)
647 t = &sc->t[i];
648 if (sc->legacy_route && i < 2)
687 sc->useirq |= (1 << i);
690 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
691 sc->legacy_route = 0;
692 if (sc->legacy_route)
693 hpet_enable(sc);
695 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
700 t = &sc->t[i];
706 sc->t[pcpu_master].
714 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
715 sc->irq = -1;
717 if (sc->useirq) {
721 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
722 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
723 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
724 if (sc->intr_res == NULL)
726 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
727 hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
730 sc->irq = rman_get_start(sc->intr_res);
732 bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
737 t = &sc->t[i];
742 if (t->irq >= 0 && sc->legacy_route && i < 2) {
753 bus_write_4(sc->mem_res,
755 bus_write_4(sc->mem_res,
764 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
765 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
766 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
769 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
787 t->et.et_frequency = sc->freq;
789 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
790 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
793 t->et.et_priv = &sc->t[i];
799 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid);
806 mda.mda_si_drv1 = sc;
807 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev));
809 sc->mmap_allow = 1;
811 &sc->mmap_allow);
812 sc->mmap_allow_write = 0;
814 &sc->mmap_allow_write);
818 CTLFLAG_RW, &sc->mmap_allow, 0,
823 CTLFLAG_RW, &sc->mmap_allow_write, 0,
845 // struct hpet_softc *sc;
852 // sc = device_get_softc(dev);
853 // hpet_disable(sc);
861 struct hpet_softc *sc;
866 sc = device_get_softc(dev);
867 hpet_enable(sc);
869 for (i = 0; i < sc->num_timers; i++) {
870 t = &sc->t[i];
872 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
879 bus_write_4(sc->mem_res,
881 bus_write_4(sc->mem_res,
888 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
893 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
895 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
897 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
898 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
901 t->next += sc->freq / 1024;
902 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
905 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
906 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
913 hpet_test(struct hpet_softc *sc)
923 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
925 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
927 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
934 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
937 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
944 struct hpet_softc *sc = device_get_softc(dev);
950 for (i = 0; i < sc->num_timers; i++) {
951 t = &sc->t[i];
959 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
960 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
961 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
962 hpet_enable(sc);