Lines Matching refs:block_id
56 static inline uint64_t CVMX_TRAX_BIST_STATUS(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
63 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
64 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
65 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
66 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
67 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
68 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
69 cvmx_warn("CVMX_TRAX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
70 return CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull;
73 #define CVMX_TRAX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull)
76 static inline uint64_t CVMX_TRAX_CTL(unsigned long block_id)
79 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
80 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
81 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
82 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
83 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
85 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
87 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
88 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
89 cvmx_warn("CVMX_TRAX_CTL(%lu) is invalid on this chip\n", block_id);
90 return CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull;
93 #define CVMX_TRAX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull)
96 static inline uint64_t CVMX_TRAX_CYCLES_SINCE(unsigned long block_id)
99 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
100 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
101 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
102 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
103 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
104 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
108 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
109 cvmx_warn("CVMX_TRAX_CYCLES_SINCE(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull;
113 #define CVMX_TRAX_CYCLES_SINCE(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull)
116 static inline uint64_t CVMX_TRAX_CYCLES_SINCE1(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
122 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
123 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
124 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
125 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
126 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
127 cvmx_warn("CVMX_TRAX_CYCLES_SINCE1(%lu) is invalid on this chip\n", block_id);
128 return CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull;
131 #define CVMX_TRAX_CYCLES_SINCE1(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull)
134 static inline uint64_t CVMX_TRAX_FILT_ADR_ADR(unsigned long block_id)
137 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
138 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
139 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
140 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
141 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
142 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
143 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
145 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
146 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
147 cvmx_warn("CVMX_TRAX_FILT_ADR_ADR(%lu) is invalid on this chip\n", block_id);
148 return CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull;
151 #define CVMX_TRAX_FILT_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull)
154 static inline uint64_t CVMX_TRAX_FILT_ADR_MSK(unsigned long block_id)
157 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
158 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
159 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
160 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
161 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
162 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
163 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
164 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
166 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
167 cvmx_warn("CVMX_TRAX_FILT_ADR_MSK(%lu) is invalid on this chip\n", block_id);
168 return CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull;
171 #define CVMX_TRAX_FILT_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull)
174 static inline uint64_t CVMX_TRAX_FILT_CMD(unsigned long block_id)
177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
179 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
183 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
184 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
185 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
186 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
187 cvmx_warn("CVMX_TRAX_FILT_CMD(%lu) is invalid on this chip\n", block_id);
188 return CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull;
191 #define CVMX_TRAX_FILT_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull)
194 static inline uint64_t CVMX_TRAX_FILT_DID(unsigned long block_id)
197 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
198 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
199 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
200 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
201 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
203 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
205 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
206 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
207 cvmx_warn("CVMX_TRAX_FILT_DID(%lu) is invalid on this chip\n", block_id);
208 return CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull;
211 #define CVMX_TRAX_FILT_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull)
214 static inline uint64_t CVMX_TRAX_FILT_SID(unsigned long block_id)
217 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
218 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
219 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
220 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
221 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
222 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
223 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
224 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
226 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
227 cvmx_warn("CVMX_TRAX_FILT_SID(%lu) is invalid on this chip\n", block_id);
228 return CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull;
231 #define CVMX_TRAX_FILT_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull)
234 static inline uint64_t CVMX_TRAX_INT_STATUS(unsigned long block_id)
237 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
238 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
239 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
244 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
245 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
246 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
247 cvmx_warn("CVMX_TRAX_INT_STATUS(%lu) is invalid on this chip\n", block_id);
248 return CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull;
251 #define CVMX_TRAX_INT_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull)
254 static inline uint64_t CVMX_TRAX_READ_DAT(unsigned long block_id)
257 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
258 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
259 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
260 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
261 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
262 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
265 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
266 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
267 cvmx_warn("CVMX_TRAX_READ_DAT(%lu) is invalid on this chip\n", block_id);
268 return CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull;
271 #define CVMX_TRAX_READ_DAT(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull)
274 static inline uint64_t CVMX_TRAX_READ_DAT_HI(unsigned long block_id)
277 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
278 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
279 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
280 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
281 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
282 cvmx_warn("CVMX_TRAX_READ_DAT_HI(%lu) is invalid on this chip\n", block_id);
283 return CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull;
286 #define CVMX_TRAX_READ_DAT_HI(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull)
289 static inline uint64_t CVMX_TRAX_TRIG0_ADR_ADR(unsigned long block_id)
292 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
293 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
294 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
295 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
296 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
297 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
298 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
299 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
301 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
302 cvmx_warn("CVMX_TRAX_TRIG0_ADR_ADR(%lu) is invalid on this chip\n", block_id);
303 return CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull;
306 #define CVMX_TRAX_TRIG0_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull)
309 static inline uint64_t CVMX_TRAX_TRIG0_ADR_MSK(unsigned long block_id)
312 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
313 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
314 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
316 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
317 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
318 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
319 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
320 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
321 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
322 cvmx_warn("CVMX_TRAX_TRIG0_ADR_MSK(%lu) is invalid on this chip\n", block_id);
323 return CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull;
326 #define CVMX_TRAX_TRIG0_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull)
329 static inline uint64_t CVMX_TRAX_TRIG0_CMD(unsigned long block_id)
332 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
333 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
334 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
335 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
336 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
337 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
338 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
339 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
340 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
341 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
342 cvmx_warn("CVMX_TRAX_TRIG0_CMD(%lu) is invalid on this chip\n", block_id);
343 return CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull;
346 #define CVMX_TRAX_TRIG0_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull)
349 static inline uint64_t CVMX_TRAX_TRIG0_DID(unsigned long block_id)
352 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
353 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
354 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
355 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
357 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
358 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
359 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
361 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
362 cvmx_warn("CVMX_TRAX_TRIG0_DID(%lu) is invalid on this chip\n", block_id);
363 return CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull;
366 #define CVMX_TRAX_TRIG0_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull)
369 static inline uint64_t CVMX_TRAX_TRIG0_SID(unsigned long block_id)
372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
373 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
374 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
379 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
380 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
381 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
382 cvmx_warn("CVMX_TRAX_TRIG0_SID(%lu) is invalid on this chip\n", block_id);
383 return CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull;
386 #define CVMX_TRAX_TRIG0_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull)
389 static inline uint64_t CVMX_TRAX_TRIG1_ADR_ADR(unsigned long block_id)
392 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
393 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
394 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
395 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
396 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
397 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
398 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
399 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
400 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
401 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
402 cvmx_warn("CVMX_TRAX_TRIG1_ADR_ADR(%lu) is invalid on this chip\n", block_id);
403 return CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull;
406 #define CVMX_TRAX_TRIG1_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull)
409 static inline uint64_t CVMX_TRAX_TRIG1_ADR_MSK(unsigned long block_id)
412 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
413 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
414 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
415 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
416 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
417 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
418 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
419 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
420 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
421 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
422 cvmx_warn("CVMX_TRAX_TRIG1_ADR_MSK(%lu) is invalid on this chip\n", block_id);
423 return CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull;
426 #define CVMX_TRAX_TRIG1_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull)
429 static inline uint64_t CVMX_TRAX_TRIG1_CMD(unsigned long block_id)
432 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
433 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
434 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
435 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
436 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
437 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
438 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
439 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
440 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
441 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
442 cvmx_warn("CVMX_TRAX_TRIG1_CMD(%lu) is invalid on this chip\n", block_id);
443 return CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull;
446 #define CVMX_TRAX_TRIG1_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull)
449 static inline uint64_t CVMX_TRAX_TRIG1_DID(unsigned long block_id)
452 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
453 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
454 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
455 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
456 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
457 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
458 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
459 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
460 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
461 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
462 cvmx_warn("CVMX_TRAX_TRIG1_DID(%lu) is invalid on this chip\n", block_id);
463 return CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull;
466 #define CVMX_TRAX_TRIG1_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull)
469 static inline uint64_t CVMX_TRAX_TRIG1_SID(unsigned long block_id)
472 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
473 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
474 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
475 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
476 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
477 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
478 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
479 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
480 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) ||
481 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
482 cvmx_warn("CVMX_TRAX_TRIG1_SID(%lu) is invalid on this chip\n", block_id);
483 return CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull;
486 #define CVMX_TRAX_TRIG1_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull)