contrib/octeon-sdk/cvmx-stxx-defs.h

56 static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
59 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
60 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
61 		cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id);
62 	return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
68 static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
71 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
72 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
73 		cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
74 	return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
80 static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
83 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
84 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
85 		cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
86 	return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
92 static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
95 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
96 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
97 		cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id);
98 	return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
104 static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
107 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
108 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
109 		cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id);
110 	return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
116 static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
119 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
120 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
121 		cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
122 	return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull;
125 #define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
128 static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
131 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
132 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
133 		cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id);
134 	return CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull;
137 #define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
140 static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
143 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
144 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
145 		cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
146 	return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull;
149 #define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
152 static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
155 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
156 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
157 		cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id);
158 	return CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull;
161 #define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
164 static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
167 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
168 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
169 		cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
170 	return CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
173 #define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
176 static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
179 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
180 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
181 		cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id);
182 	return CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull;
185 #define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
188 static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
191 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
192 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
193 		cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
194 	return CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull;
197 #define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
200 static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
203 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
204 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
205 		cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id);
206 	return CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull;
209 #define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
212 static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
215 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
216 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
217 		cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id);
218 	return CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull;
221 #define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
224 static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
227 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
228 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
229 		cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id);
230 	return CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull;
233 #define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
236 static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
239 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
240 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
241 		cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id);
242 	return CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull;
245 #define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)