contrib/octeon-sdk/cvmx-sli-defs.h

67 static inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset)
70 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
71 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
72 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
73 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
74 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
75 		cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
76 	return 0x0000000000000050ull + ((offset) & 3) * 16;
79 #define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
126 static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
129 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
130 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
131 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
132 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
133 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
134 		cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
135 	return 0x0000000000000400ull + ((offset) & 1) * 16;
138 #define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
141 static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
144 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
145 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
146 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
147 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
148 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
149 		cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
150 	return 0x00000000000003E0ull + ((offset) & 1) * 16;
153 #define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
156 static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
159 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
160 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
161 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
162 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
163 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
164 		cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
165 	return 0x0000000000000420ull + ((offset) & 1) * 16;
168 #define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
182 static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
185 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
186 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
187 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
188 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
189 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
190 		cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
191 	return 0x0000000000000340ull + ((offset) & 1) * 16;
194 #define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
296 static inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
299 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
300 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
301 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
302 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
303 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
304 		cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
305 	return 0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12;
308 #define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
553 static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
556 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
557 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
558 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
559 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
560 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
561 		cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
562 	return 0x0000000000002400ull + ((offset) & 31) * 16;
565 #define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
568 static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
571 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
572 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
573 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
574 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
575 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
576 		cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
577 	return 0x0000000000002800ull + ((offset) & 31) * 16;
580 #define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
583 static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
586 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
587 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
588 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
589 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
590 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
591 		cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
592 	return 0x0000000000002C00ull + ((offset) & 31) * 16;
595 #define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
598 static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
601 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
602 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
603 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
604 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
605 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
606 		cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
607 	return 0x0000000000003000ull + ((offset) & 31) * 16;
610 #define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
613 static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
616 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
617 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
618 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
619 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
620 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
621 		cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
622 	return 0x0000000000003400ull + ((offset) & 31) * 16;
625 #define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
628 static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
631 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
632 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
633 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
634 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
635 		cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
636 	return 0x0000000000003800ull + ((offset) & 31) * 16;
639 #define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
642 static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
645 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
646 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
647 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
648 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
649 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
650 		cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
651 	return 0x0000000000000C00ull + ((offset) & 31) * 16;
654 #define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
657 static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
660 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
661 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
662 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
663 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
664 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
665 		cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
666 	return 0x0000000000001400ull + ((offset) & 31) * 16;
669 #define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
672 static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
675 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
676 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
677 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
678 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
679 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
680 		cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
681 	return 0x0000000000001800ull + ((offset) & 31) * 16;
684 #define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
687 static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
690 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
691 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
692 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
693 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
694 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
695 		cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
696 	return 0x0000000000001C00ull + ((offset) & 31) * 16;
699 #define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
845 static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
848 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
849 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
850 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
851 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
852 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
853 		cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
854 	return 0x0000000000002000ull + ((offset) & 31) * 16;
857 #define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
1014 static inline uint64_t CVMX_SLI_PORTX_PKIND(unsigned long offset)
1017 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
1018 		cvmx_warn("CVMX_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
1019 	return 0x0000000000000800ull + ((offset) & 31) * 16;
1022 #define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
1025 static inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
1028 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1029 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1030 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
1031 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1032 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1033 		cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
1034 	return 0x0000000000003D80ull + ((offset) & 3) * 16;
1037 #define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
4385  * The doorbell and base address offset for next read.
4391 	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR
4662  * The doorbell and base address offset for next read.
4668 	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR