contrib/octeon-sdk/cvmx-pow-defs.h

100 static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
103 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
104 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
105 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
106 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
107 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
108 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
109 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
110 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
111 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
112 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
113 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
114 		cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset);
115 	return CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8;
118 #define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
154 static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
157 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
158 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
159 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
160 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
161 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
162 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
163 		cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset);
164 	return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8;
167 #define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
203 static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
206 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
207 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
208 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
209 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
210 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
211 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
212 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
213 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
214 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
215 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
216 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
217 		cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset);
218 	return CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8;
221 #define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
224 static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
227 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
228 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
229 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
230 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
231 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
232 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
233 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
234 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
235 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
236 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
237 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
238 		cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset);
239 	return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8;
242 #define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
245 static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
248 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
249 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
250 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
251 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
252 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
253 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
254 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
255 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
256 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
257 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
258 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
259 		cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset);
260 	return CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8;
263 #define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
288 static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
291 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
292 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
293 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
294 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
295 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
296 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
297 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
298 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
299 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
300 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
301 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
302 		cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset);
303 	return CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8;
306 #define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
320 static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
323 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
324 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
325 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
326 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
327 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
328 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
329 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
330 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
331 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
332 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
333 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
334 		cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
335 	return CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8;
338 #define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
352 static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
355 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
356 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
357 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
358 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
359 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
360 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
361 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
362 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
363 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
364 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
365 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
366 		cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
367 	return CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8;
370 #define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
373 static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
376 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
377 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
378 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
379 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
380 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
381 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
382 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
383 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
384 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
385 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
386 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
387 		cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset);
388 	return CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8;
391 #define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)