contrib/octeon-sdk/cvmx-pko.c

49 #include <asm/octeon/cvmx-config.h>
56 #include "executive-config.h"
61 #include "cvmx-config.h"
290     cvmx_pko_mem_iqueue_ptrs_t config;
352         config.u64 = 0;
353 	config.s.index = queue;
354 	config.s.qid = base_queue + queue;
355 	config.s.ipid = pko_port;
356 	config.s.tail = (queue == (num_queues - 1));
357         config.s.s_tail = (queue == static_priority_end);
358         config.s.static_p = (static_priority_base >= 0);
359         config.s.static_q = (queue <= static_priority_end);
368             case 0: config.s.qos_mask = 0x00; break;
369             case 1: config.s.qos_mask = 0x01; break;
370             case 2: config.s.qos_mask = 0x11; break;
371             case 3: config.s.qos_mask = 0x49; break;
372             case 4: config.s.qos_mask = 0x55; break;
373             case 5: config.s.qos_mask = 0x57; break;
374             case 6: config.s.qos_mask = 0x77; break;
375             case 7: config.s.qos_mask = 0x7f; break;
376             case 8: config.s.qos_mask = 0xff; break;
378                 config.s.qos_mask = 0xff;
384                 config.s.qos_mask = 0xff;
422             config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7;
426         cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
487     cvmx_pko_mem_iport_ptrs_t config;
493     config.u64 = 0;
494     config.s.eid = CVMX_O68_PKO_INVALID_EID;
497         config.s.ipid = i;
498         cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
512         config.s.ipid = XIT_pko_port;
513         config.s.qos_mask = 0xff;
514         config.s.crc = __cvmx_helper_get_has_fcs(interface);
515 	config.s.min_pkt = __cvmx_helper_get_pko_padding(interface);
516         config.s.intr = __cvmx_pko_int(interface, index);
517 	config.s.eid = __cvmx_helper_cfg_pko_port_eid(XIT_pko_port);
518         config.s.pipe = (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) ? index :
520         cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
565  * output system.  This does chip global config, and should only be
571     cvmx_pko_reg_cmd_buf_t config;
579     config.u64 = 0;
580     config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
581     config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
582     cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
735 	cvmx_pko_mem_iqueue_ptrs_t config;
736 	config.u64 = 0;
739 	    config.s.qid = queue;
740             cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
746         cvmx_pko_mem_queue_ptrs_t config;
749             config.u64          = 0;
750             config.s.tail       = 1;
751             config.s.index      = 0;
752             config.s.port       = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
753             config.s.queue      = queue & 0x7f;
754             config.s.qos_mask   = 0;
755             config.s.buf_ptr    = 0;
763             cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
793     cvmx_pko_mem_queue_ptrs_t  config;
879         config.u64          = 0;
880         config.s.tail       = queue == (num_queues - 1);
881         config.s.index      = queue;
882         config.s.port       = port;
883         config.s.queue      = base_queue + queue;
885         config.s.static_p   = static_priority_base >= 0;
886         config.s.static_q   = (int)queue <= static_priority_end;
887         config.s.s_tail     = (int)queue == static_priority_end;
894             case 0: config.s.qos_mask = 0x00; break;
895             case 1: config.s.qos_mask = 0x01; break;
896             case 2: config.s.qos_mask = 0x11; break;
897             case 3: config.s.qos_mask = 0x49; break;
898             case 4: config.s.qos_mask = 0x55; break;
899             case 5: config.s.qos_mask = 0x57; break;
900             case 6: config.s.qos_mask = 0x77; break;
901             case 7: config.s.qos_mask = 0x7f; break;
902             case 8: config.s.qos_mask = 0xff; break;
904                 config.s.qos_mask = 0xff;
909                 config.s.qos_mask = 0xff;
944             config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
947             config.s.buf_ptr = 0;
955         cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);