Lines Matching refs:offset
56 static inline uint64_t CVMX_PIP_ALT_SKIP_CFGX(unsigned long offset)
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
62 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
63 cvmx_warn("CVMX_PIP_ALT_SKIP_CFGX(%lu) is invalid on this chip\n", offset);
64 return CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8;
67 #define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
82 static inline uint64_t CVMX_PIP_BSEL_EXT_CFGX(unsigned long offset)
85 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
87 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
88 cvmx_warn("CVMX_PIP_BSEL_EXT_CFGX(%lu) is invalid on this chip\n", offset);
89 return CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16;
92 #define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
95 static inline uint64_t CVMX_PIP_BSEL_EXT_POSX(unsigned long offset)
98 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
99 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
100 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
101 cvmx_warn("CVMX_PIP_BSEL_EXT_POSX(%lu) is invalid on this chip\n", offset);
102 return CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16;
105 #define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
108 static inline uint64_t CVMX_PIP_BSEL_TBL_ENTX(unsigned long offset)
111 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 511))) ||
112 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) ||
113 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 511)))))
114 cvmx_warn("CVMX_PIP_BSEL_TBL_ENTX(%lu) is invalid on this chip\n", offset);
115 return CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8;
118 #define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8)
132 static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset)
135 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
137 cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset);
138 return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8;
141 #define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8)
144 static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset)
147 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
148 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
149 cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset);
150 return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8;
153 #define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8)
156 static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
159 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
160 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
161 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
162 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
163 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
164 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
170 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
171 cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset);
172 return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8;
175 #define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8)
200 static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
203 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
205 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
206 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
207 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
208 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
209 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
210 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
211 cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset);
212 return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8;
215 #define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8)
234 static inline uint64_t CVMX_PIP_PRI_TBLX(unsigned long offset)
237 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255)))))
238 cvmx_warn("CVMX_PIP_PRI_TBLX(%lu) is invalid on this chip\n", offset);
239 return CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8;
242 #define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8)
245 static inline uint64_t CVMX_PIP_PRT_CFGBX(unsigned long offset)
248 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
249 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)) || ((offset >= 44) && (offset <= 47)))) ||
250 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
251 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
252 cvmx_warn("CVMX_PIP_PRT_CFGBX(%lu) is invalid on this chip\n", offset);
253 return CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8;
256 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
259 static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
262 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
265 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
266 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
267 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
268 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
269 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
271 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
272 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
273 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
274 cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset);
275 return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8;
278 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
281 static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
286 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
288 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
289 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
290 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
291 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
292 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
293 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
294 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
295 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
296 cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset);
297 return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8;
300 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
303 static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
306 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
307 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
308 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
309 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
310 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
311 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
312 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
313 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) ||
314 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) ||
316 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
317 cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset);
318 return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8;
321 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
324 static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
327 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
328 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
329 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
333 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
334 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
335 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
336 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
337 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
338 cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset);
339 return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8;
342 #define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8)
345 static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
348 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
349 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
350 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
351 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
352 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
353 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
354 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
355 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
357 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
358 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
359 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
360 cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset);
361 return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8;
364 #define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8)
369 static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
372 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
373 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
374 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
378 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
379 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
380 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
381 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
382 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
383 cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset);
384 return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80;
387 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
390 static inline uint64_t CVMX_PIP_STAT0_X(unsigned long offset)
393 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
394 cvmx_warn("CVMX_PIP_STAT0_X(%lu) is invalid on this chip\n", offset);
395 return CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128;
398 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
401 static inline uint64_t CVMX_PIP_STAT10_PRTX(unsigned long offset)
404 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
406 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
408 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
409 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
410 cvmx_warn("CVMX_PIP_STAT10_PRTX(%lu) is invalid on this chip\n", offset);
411 return CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16;
414 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
417 static inline uint64_t CVMX_PIP_STAT10_X(unsigned long offset)
420 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
421 cvmx_warn("CVMX_PIP_STAT10_X(%lu) is invalid on this chip\n", offset);
422 return CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128;
425 #define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
428 static inline uint64_t CVMX_PIP_STAT11_PRTX(unsigned long offset)
431 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
432 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
433 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
434 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
435 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
436 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
437 cvmx_warn("CVMX_PIP_STAT11_PRTX(%lu) is invalid on this chip\n", offset);
438 return CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16;
441 #define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
444 static inline uint64_t CVMX_PIP_STAT11_X(unsigned long offset)
447 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
448 cvmx_warn("CVMX_PIP_STAT11_X(%lu) is invalid on this chip\n", offset);
449 return CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128;
452 #define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
455 static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
458 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
459 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
460 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
461 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
462 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
463 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
464 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
465 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
466 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
467 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
468 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
469 cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset);
470 return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80;
473 #define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
476 static inline uint64_t CVMX_PIP_STAT1_X(unsigned long offset)
479 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
480 cvmx_warn("CVMX_PIP_STAT1_X(%lu) is invalid on this chip\n", offset);
481 return CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128;
484 #define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
487 static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
490 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
491 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
492 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
493 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
494 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
495 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
496 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
497 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
498 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
499 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
500 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
501 cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset);
502 return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80;
505 #define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
508 static inline uint64_t CVMX_PIP_STAT2_X(unsigned long offset)
511 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
512 cvmx_warn("CVMX_PIP_STAT2_X(%lu) is invalid on this chip\n", offset);
513 return CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128;
516 #define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
519 static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
522 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
523 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
524 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
525 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
526 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
527 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
528 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
529 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
530 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
531 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
532 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
533 cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset);
534 return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80;
537 #define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
540 static inline uint64_t CVMX_PIP_STAT3_X(unsigned long offset)
543 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
544 cvmx_warn("CVMX_PIP_STAT3_X(%lu) is invalid on this chip\n", offset);
545 return CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128;
548 #define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
551 static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
554 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
555 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
556 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
557 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
558 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
559 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
560 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
561 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
562 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
563 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
564 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
565 cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset);
566 return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80;
569 #define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
572 static inline uint64_t CVMX_PIP_STAT4_X(unsigned long offset)
575 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
576 cvmx_warn("CVMX_PIP_STAT4_X(%lu) is invalid on this chip\n", offset);
577 return CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128;
580 #define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
583 static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
586 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
587 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
588 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
589 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
590 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
591 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
592 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
593 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
594 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
595 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
596 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
597 cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset);
598 return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80;
601 #define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
604 static inline uint64_t CVMX_PIP_STAT5_X(unsigned long offset)
607 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
608 cvmx_warn("CVMX_PIP_STAT5_X(%lu) is invalid on this chip\n", offset);
609 return CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128;
612 #define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
615 static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
618 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
619 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
620 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
621 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
622 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
623 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
624 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
625 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
626 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
627 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
628 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
629 cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset);
630 return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80;
633 #define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
636 static inline uint64_t CVMX_PIP_STAT6_X(unsigned long offset)
639 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
640 cvmx_warn("CVMX_PIP_STAT6_X(%lu) is invalid on this chip\n", offset);
641 return CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128;
644 #define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
647 static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
650 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
651 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
652 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
653 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
654 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
655 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
656 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
657 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
658 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
659 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
660 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
661 cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset);
662 return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80;
665 #define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
668 static inline uint64_t CVMX_PIP_STAT7_X(unsigned long offset)
671 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
672 cvmx_warn("CVMX_PIP_STAT7_X(%lu) is invalid on this chip\n", offset);
673 return CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128;
676 #define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
679 static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
682 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
683 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
684 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
685 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
686 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
687 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
688 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
689 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
690 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
691 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
692 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
693 cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset);
694 return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80;
697 #define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
700 static inline uint64_t CVMX_PIP_STAT8_X(unsigned long offset)
703 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
704 cvmx_warn("CVMX_PIP_STAT8_X(%lu) is invalid on this chip\n", offset);
705 return CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128;
708 #define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
711 static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
714 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
715 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
716 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
717 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
718 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
719 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
720 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
721 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
722 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
723 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
724 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
725 cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset);
726 return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80;
729 #define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
732 static inline uint64_t CVMX_PIP_STAT9_X(unsigned long offset)
735 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
736 cvmx_warn("CVMX_PIP_STAT9_X(%lu) is invalid on this chip\n", offset);
737 return CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128;
740 #define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
744 static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
747 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
748 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
749 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
750 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
751 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
752 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
753 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
754 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
755 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
757 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
758 cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset);
759 return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32;
762 #define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
765 static inline uint64_t CVMX_PIP_STAT_INB_ERRS_PKNDX(unsigned long offset)
768 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
769 cvmx_warn("CVMX_PIP_STAT_INB_ERRS_PKNDX(%lu) is invalid on this chip\n", offset);
770 return CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32;
773 #define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
776 static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
779 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
780 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
781 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
782 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
783 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
784 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
785 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
786 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
787 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
788 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
789 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
790 cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset);
791 return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32;
794 #define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
797 static inline uint64_t CVMX_PIP_STAT_INB_OCTS_PKNDX(unsigned long offset)
800 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
801 cvmx_warn("CVMX_PIP_STAT_INB_OCTS_PKNDX(%lu) is invalid on this chip\n", offset);
802 return CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32;
805 #define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
808 static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
811 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
812 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
813 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
814 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
815 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
816 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
817 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
818 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
819 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
820 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
821 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
822 cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset);
823 return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32;
826 #define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
829 static inline uint64_t CVMX_PIP_STAT_INB_PKTS_PKNDX(unsigned long offset)
832 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
833 cvmx_warn("CVMX_PIP_STAT_INB_PKTS_PKNDX(%lu) is invalid on this chip\n", offset);
834 return CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32;
837 #define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
851 static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
854 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
855 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
856 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
857 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
858 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
859 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
860 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
861 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) ||
862 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) ||
863 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) ||
864 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
865 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
866 cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset);
867 return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8;
870 #define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
876 static inline uint64_t CVMX_PIP_VLAN_ETYPESX(unsigned long offset)
879 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
880 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
881 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
882 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
883 cvmx_warn("CVMX_PIP_VLAN_ETYPESX(%lu) is invalid on this chip\n", offset);
884 return CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8;
887 #define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8)
890 static inline uint64_t CVMX_PIP_XSTAT0_PRTX(unsigned long offset)
893 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
894 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
895 cvmx_warn("CVMX_PIP_XSTAT0_PRTX(%lu) is invalid on this chip\n", offset);
896 return CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40;
899 #define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
902 static inline uint64_t CVMX_PIP_XSTAT10_PRTX(unsigned long offset)
905 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
906 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
907 cvmx_warn("CVMX_PIP_XSTAT10_PRTX(%lu) is invalid on this chip\n", offset);
908 return CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40;
911 #define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
914 static inline uint64_t CVMX_PIP_XSTAT11_PRTX(unsigned long offset)
917 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
918 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
919 cvmx_warn("CVMX_PIP_XSTAT11_PRTX(%lu) is invalid on this chip\n", offset);
920 return CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40;
923 #define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
926 static inline uint64_t CVMX_PIP_XSTAT1_PRTX(unsigned long offset)
929 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
930 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
931 cvmx_warn("CVMX_PIP_XSTAT1_PRTX(%lu) is invalid on this chip\n", offset);
932 return CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40;
935 #define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
938 static inline uint64_t CVMX_PIP_XSTAT2_PRTX(unsigned long offset)
941 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
942 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
943 cvmx_warn("CVMX_PIP_XSTAT2_PRTX(%lu) is invalid on this chip\n", offset);
944 return CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40;
947 #define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
950 static inline uint64_t CVMX_PIP_XSTAT3_PRTX(unsigned long offset)
953 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
954 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
955 cvmx_warn("CVMX_PIP_XSTAT3_PRTX(%lu) is invalid on this chip\n", offset);
956 return CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40;
959 #define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
962 static inline uint64_t CVMX_PIP_XSTAT4_PRTX(unsigned long offset)
965 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
966 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
967 cvmx_warn("CVMX_PIP_XSTAT4_PRTX(%lu) is invalid on this chip\n", offset);
968 return CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40;
971 #define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
974 static inline uint64_t CVMX_PIP_XSTAT5_PRTX(unsigned long offset)
977 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
978 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
979 cvmx_warn("CVMX_PIP_XSTAT5_PRTX(%lu) is invalid on this chip\n", offset);
980 return CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40;
983 #define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
986 static inline uint64_t CVMX_PIP_XSTAT6_PRTX(unsigned long offset)
989 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
990 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
991 cvmx_warn("CVMX_PIP_XSTAT6_PRTX(%lu) is invalid on this chip\n", offset);
992 return CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40;
995 #define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
998 static inline uint64_t CVMX_PIP_XSTAT7_PRTX(unsigned long offset)
1001 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
1002 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
1003 cvmx_warn("CVMX_PIP_XSTAT7_PRTX(%lu) is invalid on this chip\n", offset);
1004 return CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40;
1007 #define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
1010 static inline uint64_t CVMX_PIP_XSTAT8_PRTX(unsigned long offset)
1013 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
1014 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
1015 cvmx_warn("CVMX_PIP_XSTAT8_PRTX(%lu) is invalid on this chip\n", offset);
1016 return CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40;
1019 #define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
1022 static inline uint64_t CVMX_PIP_XSTAT9_PRTX(unsigned long offset)
1025 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
1026 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
1027 cvmx_warn("CVMX_PIP_XSTAT9_PRTX(%lu) is invalid on this chip\n", offset);
1028 return CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40;
1031 #define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
1215 * tag, offset, and skip values to be used when using the corresponding extractor.
1228 uint64_t offset : 9; /**< Indicates offset to add to extractor mem adr
1236 uint64_t offset : 9;
2861 * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires
2897 uint64_t offset : 3; /**< Number of 8B ticks to include in workQ entry
2908 uint64_t offset : 3;