Lines Matching refs:offset
53 static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
56 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
57 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
58 cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
62 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
186 static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
191 cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
192 return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16;
195 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
198 static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
201 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
203 cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
204 return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16;
207 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
210 static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
213 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
214 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
215 cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
216 return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16;
219 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
222 static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
227 cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
228 return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16;
231 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
415 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
418 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
419 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
420 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
421 return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12;
424 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
680 static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
685 cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
686 return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16;
689 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
692 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
695 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
696 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
697 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
698 return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16;
701 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
704 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
707 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
709 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
710 return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16;
713 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
716 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
719 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
720 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
721 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
722 return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16;
725 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
728 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
731 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
732 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
733 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
734 return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16;
737 #define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
740 static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
743 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
744 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
745 cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
746 return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16;
749 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
752 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
755 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
757 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
758 return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16;
761 #define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
764 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
769 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
770 return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16;
773 #define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
776 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
779 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
780 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
781 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
782 return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16;
785 #define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
920 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
923 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
924 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
925 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
926 return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16;
929 #define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
1163 static inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
1166 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
1169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1170 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1171 cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
1172 return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16;
1175 #define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
1222 static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
1225 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1226 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1227 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1228 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1229 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1230 cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
1231 return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16;
1234 #define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
1237 static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
1240 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1241 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1242 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1243 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1244 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1245 cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
1246 return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16;
1249 #define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
1252 static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
1255 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1256 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1257 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1258 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1259 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1260 cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
1261 return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16;
1264 #define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
1278 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)
1281 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1282 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1283 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1284 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1285 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1286 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
1287 return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16;
1290 #define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
1381 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
1384 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
1385 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
1386 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
1387 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
1388 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
1389 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
1390 return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12;
1393 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
1638 static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
1641 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1642 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1643 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1644 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1645 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1646 cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
1647 return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16;
1650 #define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
1653 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
1656 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1657 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1658 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1659 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1660 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1661 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
1662 return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16;
1665 #define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
1668 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
1671 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1672 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1673 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1674 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1675 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1676 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1677 return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16;
1680 #define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
1683 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
1686 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1687 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1688 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1689 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1690 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1691 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1692 return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16;
1695 #define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
1698 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)
1701 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1702 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1703 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1704 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1705 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1706 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
1707 return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16;
1710 #define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
1713 static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)
1716 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1717 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1718 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1719 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1720 cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
1721 return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16;
1724 #define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
1727 static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
1730 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1731 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1732 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1733 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1734 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1735 cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
1736 return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16;
1739 #define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
1742 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
1745 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1746 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1747 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1748 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1749 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1750 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
1751 return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16;
1754 #define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
1757 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
1760 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1761 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1762 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1763 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1764 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1765 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1766 return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16;
1769 #define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
1772 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
1775 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1776 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1777 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1778 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1779 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1780 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1781 return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16;
1784 #define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
1930 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
1933 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1934 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1935 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1936 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1937 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1938 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
1939 return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16;
1942 #define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
2099 static inline uint64_t CVMX_PEXP_SLI_PORTX_PKIND(unsigned long offset)
2102 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
2103 cvmx_warn("CVMX_PEXP_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
2104 return CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16;
2107 #define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
2110 static inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
2113 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
2114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
2115 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
2116 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
2117 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
2118 cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
2119 return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16;
2122 #define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)