Lines Matching refs:block_id
56 static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 15)) && ((block_id <= 1))))))
64 cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
65 return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
68 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
71 static inline uint64_t CVMX_PEMX_BAR2_MASK(unsigned long block_id)
74 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
77 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
78 cvmx_warn("CVMX_PEMX_BAR2_MASK(%lu) is invalid on this chip\n", block_id);
79 return CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull;
82 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
85 static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
88 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
89 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
92 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
93 cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id);
94 return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull;
97 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
100 static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
103 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
104 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
107 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
108 cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
109 return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull;
112 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
115 static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
118 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
119 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
122 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
123 cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
124 return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull;
127 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
130 static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
133 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
134 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
137 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
138 cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id);
139 return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull;
142 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
145 static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
148 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
149 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
152 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
153 cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id);
154 return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull;
157 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
160 static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
163 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
164 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
167 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
168 cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
169 return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull;
172 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
175 static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
178 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
179 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
182 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
183 cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
184 return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull;
187 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
190 static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
193 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
194 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
197 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
198 cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
199 return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull;
202 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
205 static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
208 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
209 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
212 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
213 cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
214 return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull;
217 #define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
220 static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
223 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
227 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
228 cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
229 return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull;
232 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
235 static inline uint64_t CVMX_PEMX_INB_READ_CREDITS(unsigned long block_id)
238 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
239 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
241 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
242 cvmx_warn("CVMX_PEMX_INB_READ_CREDITS(%lu) is invalid on this chip\n", block_id);
243 return CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull;
246 #define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
249 static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
252 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
253 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
254 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
256 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
257 cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id);
258 return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull;
261 #define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
264 static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
267 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
269 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
271 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
272 cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id);
273 return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull;
276 #define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
279 static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
282 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
283 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
284 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
286 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
287 cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id);
288 return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull;
291 #define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
294 static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
297 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
298 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
299 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
301 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
302 cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
303 return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull;
306 #define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
309 static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
312 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
313 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
314 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
316 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
317 cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
318 return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull;
321 #define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
324 static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
327 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
328 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
329 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
331 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
332 cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
333 return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull;
336 #define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
339 static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
342 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
343 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
344 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
345 cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
346 return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
349 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
352 static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
355 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
357 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
358 cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
359 return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
362 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
365 static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
368 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
369 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
370 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
371 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
372 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
373 cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
374 return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull;
377 #define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)