Lines Matching refs:offset
56 static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
64 cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
65 return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
68 #define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384)
71 static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
77 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
78 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
79 cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
80 return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
83 #define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384)
86 static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
93 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
94 cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
95 return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
98 #define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384)
101 static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
104 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
108 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
109 cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
110 return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
113 #define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384)
116 static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
119 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
122 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
123 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
124 cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
125 return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
128 #define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384)
131 static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
134 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
137 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
138 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
139 cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
140 return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384;
143 #define CVMX_PCMX_RXMSK0(offset) (CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384)
146 static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
153 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
154 cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
155 return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384;
158 #define CVMX_PCMX_RXMSK1(offset) (CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384)
161 static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
164 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
168 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
169 cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
170 return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384;
173 #define CVMX_PCMX_RXMSK2(offset) (CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384)
176 static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
179 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
183 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
184 cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
185 return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384;
188 #define CVMX_PCMX_RXMSK3(offset) (CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384)
191 static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
197 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
198 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
199 cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
200 return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384;
203 #define CVMX_PCMX_RXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384)
206 static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
209 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
212 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
213 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
214 cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
215 return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384;
218 #define CVMX_PCMX_RXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384)
221 static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
227 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
228 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
229 cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
230 return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384;
233 #define CVMX_PCMX_RXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384)
236 static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
243 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
244 cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
245 return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384;
248 #define CVMX_PCMX_RXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384)
251 static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
257 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
258 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
259 cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
260 return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384;
263 #define CVMX_PCMX_RXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384)
266 static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
272 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
273 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
274 cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
275 return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384;
278 #define CVMX_PCMX_TDM_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384)
281 static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
288 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
289 cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
290 return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384;
293 #define CVMX_PCMX_TDM_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384)
296 static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
299 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
302 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
303 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
304 cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
305 return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384;
308 #define CVMX_PCMX_TXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384)
311 static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
314 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
316 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
317 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
318 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
319 cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
320 return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384;
323 #define CVMX_PCMX_TXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384)
326 static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
329 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
333 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
334 cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
335 return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384;
338 #define CVMX_PCMX_TXMSK0(offset) (CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384)
341 static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
344 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
345 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
346 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
347 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
348 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
349 cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
350 return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384;
353 #define CVMX_PCMX_TXMSK1(offset) (CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384)
356 static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
359 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
362 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
363 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
364 cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
365 return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384;
368 #define CVMX_PCMX_TXMSK2(offset) (CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384)
371 static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
374 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
378 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
379 cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
380 return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384;
383 #define CVMX_PCMX_TXMSK3(offset) (CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384)
386 static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
389 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
390 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
391 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
392 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
393 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
394 cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
395 return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384;
398 #define CVMX_PCMX_TXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384)
401 static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
404 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
406 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
408 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
409 cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
410 return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384;
413 #define CVMX_PCMX_TXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384)
416 static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
419 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
420 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
421 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
422 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
423 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
424 cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
425 return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384;
428 #define CVMX_PCMX_TXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384)
431 static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
434 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
435 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
436 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
437 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
438 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
439 cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
440 return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384;
443 #define CVMX_PCMX_TXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384)
446 static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
449 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
450 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
451 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
452 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
453 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
454 cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
455 return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384;
458 #define CVMX_PCMX_TXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384)
905 uint64_t fram : 3; /**< Frame offset | NS